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DS2155 Datasheet(PDF) 199 Page - Dallas Semiconductor |
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DS2155 Datasheet(HTML) 199 Page - Dallas Semiconductor |
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199 / 238 page ![]() DS2155 199 of 238 34. JTAG BOUNDARY SCAN ARCHITECTURE AND TEST ACCESS PORT 34.1 Description The DS2155 IEEE 1149.1 design supports the standard instruction codes SAMPLE/PRELOAD, BYPASS, and EXTEST. Optional public instructions included are HIGH-Z, CLAMP, and IDCODE (Figure 34-1.). The DS2155 contains the following features as required by IEEE 1149.1 standard test access port (TAP) and boundary scan architecture. Test Access Port TAP Controller Instruction Register Bypass Register Boundary Scan Register Device Identification Register The DS2155 is pin-compatible with the DS2152, DS21x52 (T1) and DS2154, DS21x54 (E1) SCT families. The JTAG feature uses pins that had no function in the DS2152 and DS2154. Details about boundary scan architecture and the TAP are in IEEE 1149.1-1990, IEEE 1149.1a-1993, and IEEE 1149.1b-1994. NOTE: JTAG functionality is production tested at 25C only. The TAP contains the necessary interface pins JTRST, JTCLK, JTMS, JTDI, and JTDO. See the pin descriptions in Section 4 for details. Figure 34-1. JTAG Functional Block Diagram +V BOUNDARY SCAN REGISTER IDENTIFICATION REGISTER BYPASS REGISTER INSTRUCTION REGISTER JTDI JTMS JTCLK JTRST JTDO +V +V TEST ACCESS PORT CONTROLLER MUX 10kΩ 10kΩ 10kΩ SELECT OUTPUT ENABLE |
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