LPC43S37 datasheet(56/157 Pages) NXP

56 / 157 page

LPC43S5X_S3X

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Product data sheet

Rev. 1.3 — 13 January 2020

56 of 157

NXP Semiconductors

LPC43S5x/S3x

32-bit ARM Cortex-M4/M0 microcontroller

Debug pins

DBGEN

[2]

JTAG interface control signal. Also used for boundary scan. To

use the part in functional mode, connect this pin in one of the

following ways:

• Leave DBGEN open. The DBGEN pin is pulled up

internally by a 50 kΩ resistor.

• Tie DBGEN to VDDIO.

• Pull DBGEN up to VDDIO with an external pull-up

resistor.

TCK/SWDCLK

[2]

I; F

Test Clock for JTAG interface (default) or Serial Wire (SW)

clock.

TRST

[2]

I; PU I

Test Reset for JTAG interface.

TMS/SWDIO

[2]

I; PU I

Test Mode Select for JTAG interface (default) or SW debug

data input/output.

TDO/SWO

[2]

Test Data Out for JTAG interface (default) or SW trace output.

TDI

[2]

I; PU I

Test Data In for JTAG interface.

USB0 pins

USB0_DP

[6]

I/O USB0 bidirectional D+ line. Do not add an external series

resistor.

USB0_DM

[6]

I/O USB0 bidirectional D

 line. Do not add an external series

resistor.

USB0_VBUS

[6]

[7]

I/O VBUS pin (power on USB cable). This pin includes an internal

pull-down resistor of 64 k

 (typical)  16 k.

USB0_ID

[8]

Indicates to the transceiver whether connected as an A-device

(USB0_ID LOW) or B-device (USB0_ID HIGH). For OTG this

pin has an internal pull-up resistor.

USB0_RREF

[8]

12.0 k

 (accuracy 1 %) on-board resistor to ground for current

reference.

USB1 pins

USB1_DP

F12

129

[9]

I/O USB1 bidirectional D+ line. Add an external series resistor of

 +/- 2 %.

USB1_DM

G12

E10

130

[9]

I/O USB1 bidirectional D

 line. Add an external series resistor of

 +/- 2 %.

I2C-bus pins

I2C0_SCL

L15

132

[10] I; F

I/O I2C clock input/output. Open-drain output (for I2C-bus

compliance).

I2C0_SDA

L16

133

[10] I; F

I/O I2C data input/output. Open-drain output (for I2C-bus

compliance).

Reset and wake-up pins

RESET

185

128

[11] I; IA I

External reset input: A LOW on this pin resets the device,

causing I/O ports and peripherals to take on their default

states, and processor execution to begin at address 0. This

pin does not have an internal pull-up.

Table 3.

Pin description …continued

Pin name

Description

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