LPC43S37 datasheet(96/157 Pages) NXP

96 / 157 page

LPC43S5X_S3X

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Product data sheet

Rev. 1.3 — 13 January 2020

96 of 157

NXP Semiconductors

LPC43S5x/S3x

32-bit ARM Cortex-M4/M0 microcontroller

[1]

Typical ratings are not guaranteed. The values listed are at room temperature (25

C), nominal supply voltages.

[2]

The recommended operating condition for the battery supply is VDD(REG)(3V3) > VBAT + 0.2 V. Special conditions for VDD(REG)(3V3) apply

when writing to the flash and EEPROM. See Table 16 and Table 15.

[3]

Pin VPP should either be not connected (when OTP does not need to be programmed) or tied to pins VDDIO and VDDREG to ensure

the same ramp-up time for both supply voltages.

[4]

VDD(REG)(3V3) = 3.3 V; VDD(IO) = 3.3 V; Tamb = 25 C.

[5]

PLL1 disabled; IRC running; CCLK = 12 MHz.

[6]

VBAT = 3.6 V.

[7]

Tamb = -40 C to +105 C; VDD(IO) = VDDA = 3.6 V; over entire frequency range CCLK = 12 MHz to 204 MHz; in active mode, sleep

mode; deep-sleep mode, power-down mode, and deep power-down mode.

[8]

On pin VBAT; Tamb = 25 C.

[9]

Vps corresponds to the output of the power switch (see Figure 9) which is determined by the greater of VBAT and VDD(Reg)(3V3).

[10] VDDA(3V3) = 3.3 V; Tamb = 25 C.

[11] Allowed as long as the current limit does not exceed the maximum current allowed by the device.

[12] To VSS.

[13] The values specified are simulated and absolute values.

[14] The weak pull-up resistor is connected to the VDD(IO) rail and pulls up the I/O pin to the VDD(IO) level.

[15] The input cell disables the weak pull-up resistor when the applied input voltage exceeds VDD(IO).

VIC

common-mode input

voltage

high-speed mode

50

200

500

full-speed/low-speed

mode

800

2500

chirp mode

50

600

Vi(dif)

differential input voltage

100

400

1100

USB1 pins (USB1_DP/USB1_DM)[17]

IOZ

OFF-state output

current

0 V < VI < 3.3 V

[17] --

10

A

VBUS

bus supply voltage

[18] -

5.25

VDI

differential input

sensitivity voltage

(D+)  (D)

0.2

VCM

differential common

mode voltage range

includes VDI range

0.8

2.5

Vth(rs)se

single-ended receiver

switching threshold

voltage

0.8

2.0

VOL

LOW-level output

voltage for

low-/full-speed

RL of 1.5 k to 3.6 V

0.18

VOH

HIGH-level output

voltage (driven) for

low-/full-speed

RL of 15 k to GND

2.8

3.5

Ctrans

transceiver capacitance pin to GND

ZDRV

driver output

impedance for driver

which is not high-speed

capable

with 33

 series resistor;

steady state drive

[19] 36

44.1



Table 11.

Static characteristics …continued

Tamb = 40 C to +105 C, unless otherwise specified.

Symbol

Parameter

Conditions

Min

Typ[1]

Max

Unit

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