PM5366-PI datasheet(190/267 Pages) PMC

190 / 267 page

PRELIMINARY

PM5366 TEMAP-84

DATASHEET

PMC-2010672

ISSUE 1

HIGH DENSITY 84/63 CHANNEL VT/TU MAPPER

AND M13 MULTIPLEXER

PROPRIETARY AND CONFIDENTIAL

178

Transparent VTs can float in the SBI structure in two ways. The first method uses

valid V1 and V2 pointers to indicate positive and negative pointer justifications.

The second methods uses the SBI signals SDV5, SAV5, SDPL and SAPL to

indicate rate adjustments. In the DROP bus, the TEMAP-84 will always provide

both valid pointers with valid SDV5 and SDPL signals. On the SBI Add Bus, the

TEMAP-84 needs to be configured on a per tributary basis for either transparent

VT mode. Transparent VT operation is configured on a per tributary basis via the

ETVT and ETVTPTRDIS bits in the TTMP Tributary control registers.

On the DROP BUS the TEMAP-84 is timing master as determined by the arrival

rate of data over the SBI.

On the ADD BUS the TEMAP-84 can be either the timing master or the timing

slave. When the TEMAP-84 is the timing slave it receives its transmit timing

information from the arrival rate of data across the SBI ADD bus. When the

TEMAP-84 is the timing master it signals devices on the SBI ADD bus to speed

up or slow down with the justification request signal, SAJUST_REQ. The

TEMAP-84 as timing master indicates a speedup request to a Link Layer SBI

device by asserting the justification request signal high during the V3 or H3 octet.

When this is detected by the Link Layer it will speed up the channel by inserting

extra data in the next V3 or H3 octet. The TEMAP-84 indicates a slow down

request to the Link Layer by asserting the justification request signal high during

the octet after the V3 or H3 octet. When detected by the Link Layer it will retard

the channel by leaving the octet following the next V3 or H3 octet unused. Both

advance and retard rate adjustments take place in the frame or multi-frame

following the justification request.

Arbitrary Bandwidth Support

Data streams of an arbitrary bit rate up to the capacitry of an SPE may be

transported across the SPEs to and from the Flexible Bandwidth Ports. When

one (or more) of the SBI is programmed to support this, the SAPL and SDPL

signals may be asserted and deasserted at arbitrary times to allow precise

control of the payload bit rate.

On the DROP Bus, data received on the FBWDAT[3:1] signals are collected into

complete bytes and are presented on SDDATA[7:0] with SDPL asserted high.

No flow control is implemented on the DROP bus.

On the ADD Bus, the EFWBDREQ[3:1] signals request data at a specific rate.

The data is read from a shallow FIFO. To keep the FIFO half full, the

SAJUST_REQ output is asserted to fetch data across the ADD bus. In turn, the

data source responds with data and the SAPL signal asserted an equal or less

number of cycles than SAJUST_REQ is asserted. Significant latency is

PM5366-PI Datasheet(PDF) 190 Page - PMC-Sierra, Inc

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