PM5366-PI datasheet(191/267 Pages) PMC

191 / 267 page

PRELIMINARY

PM5366 TEMAP-84

DATASHEET

PMC-2010672

ISSUE 1

HIGH DENSITY 84/63 CHANNEL VT/TU MAPPER

AND M13 MULTIPLEXER

PROPRIETARY AND CONFIDENTIAL

179

tolerated. Note that the some applications require an exact one-to-one

correspondence between SAJUST_REQ and data bytes.

SBI Link Rate Information

The TEMAP-84 SBI bus provides a method for carrying link rate information

between devices. Two methods are specified, one for T1 and E1 channels and

the second for DS3 and E3 channels. For T1 and E1, the link rate information is

always generated on the Drop bus and always ignored on the Add bus. For DS3

and E3, only the ClkRate field of the link rate byte is valid on the Drop bus and

the use is optional on the Add bus as specified by the CLK_MODE[1:0] bits of

the EXSBI Tributary Control Indirect Access Data register. Link rate information

is not available for TVTs. These methods use the reference 19.44 MHz SBI

clock and the SAC1FP frame synchronization signal to measure channel clock

ticks and clock phase for transport across the bus.

The T1 and E1 method allows for a count of the number of T1 or E1 rising clock

edges between 2 KHz SDC1FP frame pulses. This count is encoded in

ClkRate[1:0] to indicate that the nominal number of clocks, one more than

nominal or one less than nominal should be generated during the SDC1FP

period. This method also counts the number of 19.44 MHz clock rising edges

after sampling SDC1FP high to the next rising edge of the T1 or E1 clock, giving

the ability to control the phase of the generated clock. The link rate information

passed across the SBI bus via the V4 octet and is shown in Table 23.

Table 24 shows the encoding of the clock count, ClkRate[1:0], passed in the link

rate octet.

Note that while the TEMAP-84 generates valid link rate information on the SBI

Drop bus, it ignores the V4 byte on the Add bus.

PM5366-PI Datasheet(PDF) 191 Page - PMC-Sierra, Inc