PM5366-PI datasheet(209/267 Pages) PMC

209 / 267 page

PRELIMINARY

PM5366 TEMAP-84

DATASHEET

PMC-2010672

ISSUE 1

HIGH DENSITY 84/63 CHANNEL VT/TU MAPPER

AND M13 MULTIPLEXER

PROPRIETARY AND CONFIDENTIAL

197

The boundary scan architecture consists of a TAP controller, an instruction

and a boundary scan register. The TAP controller interprets the TMS input and

generates control signals to load the instruction and data registers. The

instruction register with instruction decode block is used to select the test to be

executed and/or the register to be accessed. The bypass register offers a single-

bit delay from primary input, TDI to primary output, TDO. The device

identification register contains the device identification code.

The boundary scan register allows testing of board inter-connectivity. The

boundary scan register consists of a shift register placed in series with device

inputs and outputs. Using the boundary scan register, all digital inputs can be

sampled and shifted out on primary output, TDO. In addition, patterns can be

shifted in on primary input, TDI, and forced onto all digital outputs.

12.12.1

TAP Controller

The TAP controller is a synchronous finite state machine clocked by the rising

edge of primary input, TCK. All state transitions are controlled using primary

input, TMS. The finite state machine is described below.

PM5366-PI Datasheet(PDF) 209 Page - PMC-Sierra, Inc