PM5366-PI datasheet(216/267 Pages) PMC

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PRELIMINARY

PM5366 TEMAP-84

DATASHEET

PMC-2010672

ISSUE 1

HIGH DENSITY 84/63 CHANNEL VT/TU MAPPER

AND M13 MULTIPLEXER

PROPRIETARY AND CONFIDENTIAL

204

FUNCTIONAL TIMING

13.1 DS3 Line Side Interface Timing

All functional timing diagrams assume that polarity control is not being applied to

input and output data and clock lines (i.e. polarity control bits in the TEMAP-84

registers are set to their default states).

Figure 33

- Receive Bipolar DS3 Stream

RPOS[x]

RNEG[x]

3 consec 0s

LCV

RCLK[x]

The Receive Bipolar DS3 Stream diagram (Figure 33) shows the operation of the

TEMAP-84 while processing a B3ZS encoded DS3 stream on inputs RPOS and

RNEG. It is assumed that the first bipolar violation (on RNEG) illustrated

corresponds to a valid B3ZS signature. A line code violation is declared upon

detection of three consecutive zeros in the incoming stream, or upon detection of

a bipolar violation which is not part of a valid B3ZS signature.

Figure 34

- Receive Unipolar DS3 Stream

RCLK[x]

RDATI[x] X1 BIT

RLCV[x]

X2 BIT

INFO 84

C BIT

INFO 1

INFO 2

INFO 3

INFO 4

INFO 5

OR P OR M BIT

OR F BIT

INFO 84

INFO 1

LCV INDICATION

The Receive Unipolar DS3 Stream diagram (Figure 34) shows the complete DS3

receive signal on the RDAT input. Line code violation indications, detected by an

upstream B3ZS decoder, are indicated on input RLCV. RLCV is sampled each

bit period. The PMON Line Code Violation Event Counter is incremented each

time a logic 1 is sampled on RLCV.

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