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PM5366-PI Datasheet(PDF) 220 Page - PMC-Sierra, Inc |
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PM5366-PI Datasheet(HTML) 220 Page - PMC-Sierra, Inc |
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220 / 267 page  PRELIMINARY PM5366 TEMAP-84 DATASHEET PMC-2010672 ISSUE 1 HIGH DENSITY 84/63 CHANNEL VT/TU MAPPER AND M13 MULTIPLEXER PROPRIETARY AND CONFIDENTIAL 208 13.2 DS3 and E3 System Side Interface Timing Figure 41 - Framer Mode DS3 Transmit Input Stream TDATI[x] INFO 84 TFPI/TMFPI[x] INFO 84 INFO 83 INFO 82 X1 INFO 2 INFO 1 X2 INFO 1INFO 2INFO 3 INFO 84 INFO 82 INFO 83 F4 INFO 82 INFO 83 TFPO/TMFPO[x] TICLK[x] Figure 42 - Framer Mode DS3 Transmit Input Stream With TGAPCLK TGAPCLK[x] TDATI[x] INFO 1 INFO 83 INFO 82 INFO 81 INFO 3 INFO 2 INFO 2 INFO 3 INFO 4 INFO 1 INFO 83 INFO 84 INFO 83 INFO 84 TICLK[x] INFO 1 The Framer Mode DS3 Transmit Input Stream diagram (Figure 41) shows the expected format of the inputs TDAT and TFPI/TMFPI along with TICLK and the output TFPO/TMFPO when the OPMODE_SPEx[2:0] bits are set to “DS3/E3 Framer Only mode” in the SPE Configuration registers. If the TXMFPI bit in the DS3 and E3 Master Unchannelized Interface Options register is logic 0, then TFPI is valid, and the TEMAP-84 will expect TFPI to pulse for every DS3 overhead bit with alignment to TDATI. If the TXMFPI register bit is logic 1, then TMFPI is valid, and the TEMAP-84 will expect TMFPI to pulse once every DS3 M-frame with alignment to TDATI. If the TXMFPO bit in the DS3 and E3 Master Unchannelized Interface Options register is logic 0, then TFPO is valid, and the TEMAP-84 will pulse TFPO once every 85 TICLK cycles, providing upstream equipment with a reference DS3 overhead pulse. If the TXMFPO register bit is logic 1, then TMFPO is valid and the TEMAP-84 will pulse TMFPO once every 4760 TICLK cycles, providing upstream equipment with a reference M-frame pulse. The alignment of TFPO or TMFPO is arbitrary. There is no set relationship between TFPO/TMFPO and TFPI/TMFPI. The TGAPCLK output is available in place of TFPO/TMFPO when the TXGAPEN bit in the DS3 and E3 Master Unchannelized Interface Options register is set to logic 1, as in Figure 42. TGAPCLK remains high during the overhead bit positions. |
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