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PM5366-PI Datasheet(PDF) 221 Page - PMC-Sierra, Inc

Part # PM5366-PI
Description  HIGH DENSITY 84/63 CHANNEL VT/TU MAPPER AND M13 MULTIPLEXER
PDF  267 Pages
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Manufacturer  PMC [PMC-Sierra, Inc]
Direct Link  http://www.pmc-sierra.com
Logo PMC - PMC-Sierra, Inc

PM5366-PI Datasheet(HTML) 221 Page - PMC-Sierra, Inc

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PRELIMINARY
PM5366 TEMAP-84
DATASHEET
PMC-2010672
ISSUE 1
HIGH DENSITY 84/63 CHANNEL VT/TU MAPPER
AND M13 MULTIPLEXER
PROPRIETARY AND CONFIDENTIAL
209
Figure 43
- Framer Mode DS3 Receive Output Stream
RDATO[x]
INFO 84
RFPO/RMFPO[x]
INFO 84
INFO 83
INFO 82
X1
INFO 2
INFO 1
X2
INFO 1
INFO 2
INFO 3
INFO 84
INFO 82
INFO 83
F4
INFO 82
INFO 83
ROVRHD[x]
RSCLK[x]
Figure 44
- Framer Mode DS3 Receive Output Stream with RGAPCLK
RGAPCLK[x]
RDATO[x]
INFO 84
INFO 84
INFO 83
INFO 82
INFO 2
INFO 1
INFO 1
INFO 2
INFO 3
INFO 84
INFO 82
INFO 83
INFO 82
INFO 83
INFO 84
The DS3/E3 Framer Only Mode Receive Output Stream diagram (Figure 43)
shows the format of the outputs RDATO, RFPO/RMFPO, RSCLK ROVRHD
when the OPMODE_SPEx[2:0] bits are set to “DS3/E3 Framer Only mode” in the
SPE Configuration registers. Figure 43 shows the data streams when the
TEMAP-84 is configured for the DS3 receive format. If the RXMFPO bit in the
DS3 and E3 Master Unchannelized Interface Options register is logic 0, RFPO is
valid and will pulse high for one RSCLK cycle on first bit of each M-subframe
with alignment to the RDATO data stream. If the RXMFPO register bit is a logic
1 (as shown Figure 43), RMFPO is valid and will pulse high on the X1 bit of the
RDATO data output stream. ROVRHD will be high for every overhead bit
position on the RDATO data stream. Figure 44 shows the output data stream
with RGAPCLK in place of RSCLK when the RXGAPEN bit in the DS3 and E3
Master Unchannelized Interface Options register set to logic 1. RGAPCLK
remains high during the overhead bit positions.
Figure 45
- Framer Mode G.751 E3 Transmit Input Stream
TDATI[x]
bit 1536
0
TFPI/TMFPI[x]
Nat
RAI
11
1
10
1
0
0
bit 1531
bit 1529
bit 1530
bit 1532
bit 1533
bit 1534
bit 1535
TFPO/TMFPO[x]
0
bit13
TICLK[x]



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