PM5366-PI datasheet(165/267 Pages) PMC

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PRELIMINARY

PM5366 TEMAP-84

DATASHEET

PMC-2010672

ISSUE 1

HIGH DENSITY 84/63 CHANNEL VT/TU MAPPER

AND M13 MULTIPLEXER

PROPRIETARY AND CONFIDENTIAL

153

12.2.3 19.44 MHz SBI Bus and 77.76 MHz Telecom Bus

The rising edge of LREFCLK must be aligned with a tolerance of +/- 5ns to the

rising edge of SREFCLK.

For reliable operation, the STM-1s used within the Telecom bus must be aligned

to the SREFCLK input. To this end, one may manipulate the LSTM[1:0] register

bits and the position of the LAC1 pulses. Table 15 summarizes the

combinations.

Table 16

- 19.44 MHz SBI to 77.76 MHz Telecom to Bus Alignment

Options

LSTM[1:0]

LREFCLK Cycles LAC1

sampling edge leads

SREFCLK rising edge

As alternate formulation, if LSTM[1:0] was converted to its decimal equivalent,

one would have to satisfy the constraint:

(LSTM + 1) mod 4 = Clock Cycles LAC1 leads SREFCLK

12.2.4 77.76 MHz SBI Bus and 19.44 MHz Telecom Bus

The rising edge of LREFCLK must be aligned with a tolerance of +/- 5ns to the

rising edge of SREFCLK.

For reliable operation, the STM-1s used within the SBI bus must be aligned to

LREFCLK. To this end, one may manipulate the SSTM[1:0] register bits and the

position of the SDC1FP pulses. Table 15 summarizes the combinations.

Table 17

- 77.76 MHz SBI to 19.44 MHz Telecom to Bus Alignment

Options

SSTM[1:0]

SREFCLK Cycles

SDC1FP sampling edge

leads LREFCLK rising

edge

PM5366-PI Datasheet(PDF) 165 Page - PMC-Sierra, Inc