PM5366-PI datasheet(167/267 Pages) PMC

167 / 267 page

PRELIMINARY

PM5366 TEMAP-84

DATASHEET

PMC-2010672

ISSUE 1

HIGH DENSITY 84/63 CHANNEL VT/TU MAPPER

AND M13 MULTIPLEXER

PROPRIETARY AND CONFIDENTIAL

155

Mx: M-Frame Alignment Signal

• Transmit: The TEMAP-84 generates the M-frame alignment signal (M1 = 0,

M2 = 1, M3 = 0).

• Receive: The TEMAP-84 finds M-frame alignment by searching for the F-

bits and the M-bits. Out-of-frame is removed if the M-bits are correct for

three consecutive M-frames while no discrepancies have occurred in the F-

bits. M-bit errors are counted in the DS3 PMON Framing Bit Error Event

Count registers. When one or more M-bit errors are detected in 3 out of 4

consecutive M-frames, an out-of-frame defect is asserted (if MBDIS in the

DS3 Framer Configuration register is a logic 0).

Fx: M-Subframe Alignment Signal

• Transmit: The TEMAP-84 generates the M-Subframe Alignment signal

(F1=1, F2=0, F3=0, F4=1).

• Receive: The TEMAP-84 finds M-frame alignment by searching for the F-

bits and the M-bits. Out-of-frame is removed if the M-bits are correct for

three consecutive M-frames while no discrepancies have occurred in the F-

bits. F-bit errors are counted in the DS3 PMON Framing Bit Error Event

Count registers. An out-of frame defect is asserted if 3 F-bit errors out of 8

or 16 consecutive F-bits are observed (as selected by the M3O8 bit in the

DS3 FRMR Configuration register).

Cx: C-Bit Channels

• Transmit: When configured for M23 applications, the C-bits used for

stuffing indication. When configured for C-bit parity applications, the C-bit

Parity ID bit is forced to logic 1. The second C-bit in M-subframe 1 is set to

logic 1. The third C-bit in M-subframe 1 provides a far-end alarm and

control (FEAC) signal. The FEAC channel is sourced by the DS3 XBOC

block. The 3 C-bits in M-subframe 3 carry path parity information. The

value of these 3 C-bits is the same as that of the P-bits. The 3 C-bits in M-

subframe 4 are the FEBE bits. FEBE transmission is controlled by the

DFEBE bit in the DS3 TRAN Diagnostic register and by the detection of

receive framing bit and path parity errors. The 3 C-bits in M-subframe 5

contain the 28.2 kbit/s path maintenance datalink. These bits are inserted

from the DS3 TDPR HDLC controller. The C-bits in M-subframes 2, 6, and

7 are unused and are set to logic 1.

• Receive: The CBITV register bit in the DS3 FRMR Status register is used

to report the state of the C-bit parity ID bit, and hence whether a M23 or C-

bit parity DS3 signal stream is being received. The FEAC channel on the

third C-bit in M-subframe 1 is detected by the DS3 RBOC block. Path

parity errors and detected FEBEs on the C-bits in M-subframes 3 and 4 are

reported in the DS3 PMON Path Parity Error Event Count and FEBE Event

PM5366-PI Datasheet(PDF) 167 Page - PMC-Sierra, Inc

PM5366-PI Datasheet(HTML) 167 Page - PMC-Sierra, Inc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL