PM5366-PI datasheet(170/267 Pages) PMC

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PRELIMINARY

PM5366 TEMAP-84

DATASHEET

PMC-2010672

ISSUE 1

HIGH DENSITY 84/63 CHANNEL VT/TU MAPPER

AND M13 MULTIPLEXER

PROPRIETARY AND CONFIDENTIAL

158

Figure 13

- FER Count vs. BER (E1 mode)

100

150

200

250

Average Count Over

Many 1 Second Intervals

Framing Bit Error Count Per Second

Since the maximum number of CRC sub-multiframes that can occur in one

second is 1000, the 10-bit FEBE and CRCE counters cannot saturate in one

second. Despite this, there is not a linear relationship between BER and CRC-4

block errors due to the nature of the CRC-4 calculation. At BERs below 10-4,

there tends to be no more than one bit error per sub-multiframe, so the number

of CRC-4 errors is generally equal to the number of bit errors, which is directly

related to the BER. However, at BERs above 10-4, each CRC-4 error is often

due to more than one bit error. Thus, the relationship between BER and CRCE

count becomes non-linear above a 10-4 BER. This must be taken into account

when using CRC-4 counts to determine the BER. Since FEBEs are indications of

CRCEs at the far end, and are accumulated identically to CRCEs, the same

explanation holds for the FEBE event counter.

The bit error rate for E1 can be calculated from the one-second PMON CRCE

count by the following equation:

Bit Error Rate = 1 - 10

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256

8000

log

CRCE

PM5366-PI Datasheet(PDF) 170 Page - PMC-Sierra, Inc