PM5366-PI datasheet(174/267 Pages) PMC

174 / 267 page

PRELIMINARY

PM5366 TEMAP-84

DATASHEET

PMC-2010672

ISSUE 1

HIGH DENSITY 84/63 CHANNEL VT/TU MAPPER

AND M13 MULTIPLEXER

PROPRIETARY AND CONFIDENTIAL

162

warning of an underrun is given. The FULLE, LFILLE, OVRE, and UDRE bits

are all set to logic 1 so an interrupt on INTB is generated upon detection of a

FIFO full state, a FIFO depth below the lower limit threshold, a FIFO overrun, or

a FIFO underrun. The following procedure should be followed to transmit HDLC

packets:

1. Wait for a complete packet to be transmitted. Once data is available to be

transmitted, then go to step 2.

2. Write the data byte to the TDPR Transmit Data register.

3. If all bytes of the packet have been written to the Transmit Data register, then

set the EOM bit in the TDPR Configuration register to logic 1. Go to step 1.

4. If there are more bytes in the packet to be sent, then go to step 2.

While performing steps 1 to 4, the processor should monitor for interrupts

generated by the TDPR. When an interrupt is detected, the TDPR Interrupt

Routine detailed in the following text should be followed immediately.

The TDPR will force transmission of the packet information when the FIFO depth

exceeds the threshold programmed with the UTHR[6:0] bits in the TDPR Upper

Transmit Threshold register. Unless an error condition occurs, transmission will

not stop until the last byte of all complete packets is transmitted and the FIFO

depth is at or below the threshold limit. The user should watch the FULLI and

LFILLI interrupts to prevent overruns and underruns.

TDPR Interrupt Routine:

Upon assertion of INTB, the source of the interrupt must first be identified by

reading the TEMAP-84 Master Interrupt Source register (0020H) followed by

reading one of the second level master interrupt source registers T1E1INT1,

T1E1INT2, T1E1INT3, T1E1INT4 or DS3INT. Once the source of the interrupt

has been identified as the TDPR in use, then the following procedure should be

carried out:

1. Read the TDPR Interrupt Status register.

2. If UDRI=1, then the FIFO has underrun and the last packet transmitted has

been corrupted and needs to be retransmitted. When the UDRI bit transitions

to logic 1, one Abort sequence and continuous flags will be transmitted. The

TDPR FIFO is held in reset state. To re-enable the TDPR FIFO and to clear

the underrun, the TDPR Interrupt Status/UDR Clear register should be written

with any value.

PM5366-PI Datasheet(PDF) 174 Page - PMC-Sierra, Inc

PM5366-PI Datasheet(HTML) 174 Page - PMC-Sierra, Inc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL