PM5366-PI datasheet(177/267 Pages) PMC

177 / 267 page

PRELIMINARY

PM5366 TEMAP-84

DATASHEET

PMC-2010672

ISSUE 1

HIGH DENSITY 84/63 CHANNEL VT/TU MAPPER

AND M13 MULTIPLEXER

PROPRIETARY AND CONFIDENTIAL

165

status is written into the FIFO. This is done to provide alignment of link down

status with the data read from the FIFO. It is up to the controlling processor to

check the COLS bit in the RDLC Status register for a change in the link status. If

the COLS bit is set to logic 1, the FIFO must be emptied to determine the current

link status. The first flag and abort status encoded in the PBS bits is used to set

and clear a Link Active software flag.

When the last byte of a properly terminated packet is received, an interrupt is

generated. While the RDLC Status register is being read the PKIN bit will be

logic 1. This can be a signal to the external processor to empty the bytes

remaining in the FIFO or to just increment a number-of-packets-received count

and wait for the FIFO to fill to a programmable level. Once the RDLC Status

read immediately after the last packet byte is read from the FIFO, the PBS[2] bit

will be logic 1 and the CRC and non-integer byte status can be checked by

reading the PBS[1:0] bits.

When the FIFO fill level is exceeded, an interrupt is generated. The FIFO must

be emptied to remove this source of interrupt.

The RDLC can be used in a polled or interrupt driven mode for the transfer of

frame data. In the polled mode, the processor controlling the RDLC must

periodically read the RDLC Status register to determine when to read the RDLC

Data register. In the interrupt driven mode, the processor controlling the RDLC

uses the TEMAP-84 INTB output and the TEMAP-84 Master Interrupt Source

registers to determine when to read the RDLC Data register.

In the case of interrupt driven data transfer from the RDLC to the processor, the

INTB output of the TEMAP-84 is connected to the interrupt input of the

processor. The processor interrupt service routine verifies what block generated

the interrupt by reading the TEMAP-84 Master Interrupt Source register followed

by one of the second level master interrupt source registers to identify one of

the 3 HDLC receivers as the interrupt source. Once it has identified that the

RDLC has generated the interrupt, it processes the data in the following order:

1. Read the RDLC Status register. The INTR bit should be logic 1.

2. If OVR = 1, then discard the last frame and go to step 1. Overrun causes a

reset of FIFO pointers. Any packets that may have been in the FIFO are lost.

3. If COLS = 1, then set the EMPTY FIFO software flag.

4. If PKIN = 1, increment the PACKET COUNT. If the FIFO is desired to be

emptied as soon as a complete packet is received, set the EMPTY FIFO

PM5366-PI Datasheet(PDF) 177 Page - PMC-Sierra, Inc

PM5366-PI Datasheet(HTML) 177 Page - PMC-Sierra, Inc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL