PM5366-PI datasheet(175/267 Pages) PMC

175 / 267 page

PRELIMINARY

PM5366 TEMAP-84

DATASHEET

PMC-2010672

ISSUE 1

HIGH DENSITY 84/63 CHANNEL VT/TU MAPPER

AND M13 MULTIPLEXER

PROPRIETARY AND CONFIDENTIAL

163

3. If OVRI=1, then the FIFO has overflowed. The packet of which the last byte

written into the FIFO belongs to, has been corrupted and must be

retransmitted. Other packets in the FIFO are not affected. Either a timer can

be used to determine when sufficient bytes are available in the FIFO or the

user can wait until the LFILLI interrupt is set, indicating that the FIFO depth is

at the lower threshold limit.

If the FIFO overflows on the packet currently being transmitted (packet is

greater than 128 bytes long), OVRI is set, an Abort signal is scheduled to be

transmitted, the FIFO is emptied, and then flags are continuously sent until

there is data to be transmitted. The FIFO is held in reset until a write to the

TDPR Transmit Data register occurs. This write contains the first byte of the

next packet to be transmitted.

4. If FULLI=1 and FULL=1, then the TDPR FIFO is full and no further bytes can

be written. When in this state, either a timer can be used to determine when

sufficient bytes are available in the FIFO or the user can wait until the LFILLI

interrupt is set, indicating that the FIFO depth is at the lower threshold limit.

If FULLI=1 and FULL=0, then the TDPR FIFO had reached the FULL state

earlier, but has since emptied out some of its data bytes and now has space

available in its FIFO for more data.

5. If LFILLI=1 and BLFILL=1, then the TDPR FIFO depth is below its lower

threshold limit. If there is more data to transmit, then it should be written to

the TDPR Transmit Data register before an underrun occurs. If there is no

more data to transmit, then an EOM should be set at the end of the last

packet byte. Flags will then be transmitted once the last packet has been

transmitted.

If LFILLI=1 and BLFILL=0, then the TDPR FIFO had fallen below the lower-

threshold state earlier, but has since been refilled to a level above the lower-

threshold level.

Polling Mode:

The TDPR automatically transmits a packet once it is completely written into the

TDPR FIFO. The TDPR also begins transmission of bytes once the FIFO level

exceeds the programmable Upper Transmit Threshold. The CRC bit can be set

to logic 1 so that the FCS is generated and inserted at the end of a packet. The

TDPR Lower Interrupt Threshold should be set to such a value that sufficient

warning of an underrun is given. The FULLE, LFILLE, OVRE, and UDRE bits

are all set to logic 0 since packet transmission is set to work with a periodic

polling procedure. The following procedure should be followed to transmit HDLC

packets:

PM5366-PI Datasheet(PDF) 175 Page - PMC-Sierra, Inc

PM5366-PI Datasheet(HTML) 175 Page - PMC-Sierra, Inc

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