PM7344 datasheet(222/293 Pages) PMC

222 / 293 page

PM7344 S/UNI-MPH

DATA SHEET

PMC-950449

ISSUE 6

MULTI-PHY USER NETWORK INTERFACE

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE

206

Registers 088H, 188H, 288H and 388H: TXCP Control

Bit

Type

Function

Default

Bit 7

R/W

HCSINS

Bit 6

R/W

HCSDQDB

Bit 5

R/W

HCSADD

Bit 4

R/W

FIFODP[1]

Bit 3

R/W

FIFODP[0]

Bit 2

R/W

SCR

Bit 1

R/W

DHCS

Bit 0

R/W

FIFORST

FIFORST:

The FIFORST bit is used to reset the transmit FIFO. When a logic 1 is

written to FIFORST, the FIFO is immediately emptied, and idle/unassigned

cells are transmitted. When a logic 0 is written to FIFORST, the transmit

FIFO operates normally.

DHCS:

The DHCS bit controls the insertion of header check sequence (HCS) errors

in the transmit stream. When a logic 1 is written to DHCS, a single HCS error

is inserted in each transmitted cell. When a logic 0 is written to DHCS, the

HCS is calculated and inserted normally.

SCR:

The SCR bit controls cell payload scrambling using the self synchronizing

polynomial x43 + 1. When a logic 1 is written to SCR, payload scrambling is

enabled. When a logic 0 is written to SCR, payloads are transmitted

unscrambled.

FIFODP[1:0]:

The FIFODP[1:0] bits determine the transmit FIFO cell depth. FIFO depth

control may be important in systems where the cell latency through the

S/UNI-MPH must be minimized. When the FIFO is filled to the specified

depth, the transmit FIFO full signal, TCA[x] is logic 0. TCA[x] is asserted only

after a complete cell has been read out; therefore, the current cell being read

is included in the count. The selectable FIFO cell depths are shown in the

following table:

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