TPS35 datasheet(5/43 Pages) TI

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Table 5-1. Pin Functions

NAME

PIN NUMBER

I/O

DESCRIPTION

PINOUT

CRST

—

Programmable reset timeout pin. Connect a capacitor

between this pin and GND to program the reset timeout

period. See Section 7.3.4 for more details.

CWD

—

Programmable watchdog timeout input. Watchdog timeout

is set by connecting a capacitor between this pin and

ground. See Section 7.3.2.1 for more details.

GND

—

Ground pin

—

Manual reset pin. A logic low on this pin asserts the

RESET. See Section 7.3.3 for more details.

RESET

Reset output. Connect RESET to VDD using a pull up

resistance when using open drain output. RESET is

asserted when the voltage at the VDD pin goes below the

undervoltage threshold (VIT-) or MR pin is driven LOW. For

pinout options which do not support independent WDO pin,

RESET is also asserted for watchdog error. See Section

7.3.4 for more details.

SET0

—

Logic input. SET0, SET1, and WD-EN pins select the

watchdog and enable-disable the watchdog; see Section

7.3.2.4 for more details.

SET1

—

Logic input. SET0, SET1, and WD-EN pins select the

watchdog and enable-disable the watchdog; see Section

7.3.2.4 for more details.

VDD

Supply voltage pin. For noisy systems, connecting a 0.1-

µF bypass capacitor is recommended.

WD-EN

—

Logic input. Logic high input enables the watchdog

monitoring feature. See Section 7.3.2.2 for more details.

WDI

Watchdog input. A falling transition (edge) must occur at

this pin before the timeout expires in order for RESET /

WDO to not assert. See Section 7.3.2 for more details.

WDO

—

Watchdog output. Connect WDO to VDD using pull up

resistance when using open drain output. WDO asserts

when a watchdog error occurs. WDO only asserts when

RESET is high. When a watchdog error occurs, WDO

asserts for the set RESET timeout delay (tD). When

RESET is asserted, WDO is deasserted and watchdog

functionality is disabled. See Section 7.3.4 for more

details.

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TPS35

SNVSCF5A – JUNE 2023 – REVISED DECEMBER 2023

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