using Equation 4, the part number is reduced to TPS35xx13xxxxxxx. Since the hysteresis is 5% typical, the

positive-going threshold voltage, VIT+, is 1.73 V.

8.2.1.2.2 Meeting the Watchdog Timeout Period

The watchdog timeout design requirement can be met either by using a fixed-timeout version of the TPS35 or

by connecting a capacitor between the CWD pin and GND. The typical values can be met with preprogrammed

fixed time options, hence a pinout offering fixed time options is selected. Please see the Timing Requirements

for a list of fixed timeouts. If using the CWD feature, pinout A or B must be used; please refer to tWD Timer for

instructions on how to program the timout period. The design requirement in this example is tWD = 1.6 s. This is

one of the fixed timeout options offered by pinout C or D or J. Thus the possible variant option is narrowed down

to TPS35Cx13KAxDDFR.

8.2.1.2.3 Setting the Reset Delay

The reset delay requirement can be met either by using a fixed-timeout version of the TPS35 or by connecting

a capacitor between the CRST pin and GND. The typical values can be met with preprogrammed fixed time

options, hence a pinout offering fixed time options is selected. Please see the Timing Requirements for a list of

fixed timeouts. If using the CRST feature, pinout A or B must be used; please refer to the Timing Specifications

for instructions on how to program the timout period. The design requirement in this example is tD = 200 ms.

Thus the possible variant option is narrowed down to TPS35Cx13KAGDDFR.

8.2.1.2.4 Setting the Startup Delay and Output Topology

The startup delay and output topology are set by the device variant. Please refer to Device Comparison for

the possible options. A minimum startup delay of 700 ms and open-drain output are desired, thus Option

D, 1 s typical startup delay and open-drain active-low, is selected. Thus the option suitable to meet design

requirements is TPS35CD13KAGDDFR.

8.2.1.2.5 Calculating the RESET Pullup Resistor

The TPS35 uses an open-drain configuration for the RESET output, as shown in Figure 8-2.When the FET is

off, the resistor pulls the drain of the transistor to VDD and when the FET is turned on, the FET pulls the output

to ground, thus creating an effective resistor divider. The resistors in this divider must be chosen to make sure

that VOL is below its maximum value. To choose the proper pullup resistor, there are three key specifications

to keep in mind: the pullup voltage (VPU), the recommended maximum RESET pin current (IRST), and VOL. The

maximum VOL is 0.3 V, meaning that the effective resistor divider created must be able to bring the voltage

on the reset pin below 0.3 V with IRST kept below 2 mA for VDD ≥ 3 V and 500 μA for VDD = 1.5 V. For this

example, with a VPU =VDD = 1.5 V, a resistor must be chosen to keep IRST below 500 μA because this value is

the maximum consumption current allowed. To make sure this specification is met, a pullup resistor value of 10

kΩ was selected, which sinks a maximum of 180 μA when RESET is asserted.

RESET

VDD

RESET

CONTROL

Figure 8-2. Open-Drain RESET Configuration

8.3 Power Supply Recommendations

This device is designed to operate from an input supply with a voltage range between 1.04 V and 6 V. An input

supply capacitor is not required for this device; however, if the input supply is noisy, then good analog practice is

to place a 0.1-µF capacitor between the VDD pin and the GND pin.

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TPS35

SNVSCF5A – JUNE 2023 – REVISED DECEMBER 2023

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