HV7358 datasheet(21/50 Pages) MICROCHIP

21 / 50 page

 2018 Microchip Technology Inc.

DS20005918A-page 21

HV7358

TRIGP

TRIGN

TX Trigger Inputs: TRIGP is active-high. The inputs can be driven by LVDS-2.5V or

BLVDS-2.5V via DC coupled. They can also be driven by LVDS-1.8V/2.5V via AC

coupled. In the differential input cases, a 100Ω LVDS termination resistor must connect

to the input pin pair differentially. A single TRIGP or TRIGN can also be driven by

LVCOM-2.5 single-ended output, with biasing the other input to 1.25 VDC, and a bypass

capacitor to GND.

TXRW

If TXRW = 0, the Chip is in SPI or I2C Read/Write mode; if TXRW = 1, it is in TXCH or

RXCH mode: TXRW rise edge will set all the launch counters, and reset the TXCH and

RXCH state machine for ready to launch.

CW Enable Logic Input: CW = 1 for CW mode, CW = 0 for B mode.

INV

Pulse Inversion Logic Input Selects the Polarity of the First Transmit Pulse: If INV = 1,

the first transmit pulse is a negative pulse. If INV = 0, the first transmit pulse is a positive

pulse. INV also selects the state of the transmitter output pins when the device is

disabled. When EN = 0 and INV = 1, all the transmitter output pins are high-Z. If EN = 0

and INV = 0, all the transmitter output pins are grounded.

SCL

I2C Clock Input: Must pull up to 3.3V with a 2.2 kΩ resistor.

SDA

I2C Data Input: Must pull up to 3.3V with a 2.2 kΩ resistor.

D1, D2, D3

A0, A1, A2 I2C Device’s Address Inputs: For selecting up to eight different I2C interfaces on the

same bus.

SDLY

If SDLY = 0, the SPI Writes to the Registers of DLYch[11:0], TLPch[6:0] and TLNch[6:0]:

The SPI performs a 26-bit long word data transfer per channel. When SDLY = 1, the SPI

writes the Delay registers, DLYch[11:0] only. The SPI performs a 12-bit word data

transfer per channel.

LPWM

SPI Register Block Select Pin: If LPWM = 0, the SPI write or TXCH launch selects the

global register block, which consists of four wave pattern parameters of pulse width,

global PWM time-off and launch pulse number in a TXCH burst. If LPWM = 1, select the

local per channel different PWM Time-Off and Beamforming Delay registers for the SPI

write or TXCH launch.

LCKD

PLL Locked Indicator Open-Drain Output: The LOCK output is active-high when the PLL

is locked. Alternatively, the PLL locking status can be read from the I2C Status register.

Leave this pin open (NC) when not used.

A6, A11, B6,

B11

VSUB

The substrate of the die must be grounded for good RF and DC (0V) point of view.

OTPN

Overtemperature or Undervoltage Flag: This pin is an open-drain output. OTPN = 0

when an overtemperature or undervoltage event happens. The error information will be

logged in the I2C Flag register at ADDR = 01h. The open-drain output of the OTPN pin

requires an external pull-up resistor. Leave this pin open (NC) when it is not used.

ETO

End-of-Transmit Open-Drain Output: ETO = 1 when all the TXCH have finished the TXCH

launch and are ready for the next launch. The next TRIG rise edge resets ETO = 0. The

initial power-on ETO status is high. The open-drain output of the ETO pin requires a

pull-up resistor to VLL. Leave this pin open (NC) when it is not used.

ETI

End-of-Transmit Input: Pull ETI = 1 when all the TXCH on board have finished the TXCH

launch and are ready for the next trigger. The ETI pin can be directly connected to the

ETO pin with a pull-up resistor to VLL. Connect the ETI pin to GND when it is not used.

RSTN

Chip Hard Reset Pin, Active-Low: When VLL and VDD are powered on, EN = 1 and

RSTN = 0. All registers will be reset into the default values; all TXCH outputs will be

high-Z.

R6, C7, C8,

D8, E8, F8,

L8, M8, N8,

P8, C6

DNC1-11

Do Not Connect: These pins are internally connected for I2C manufacture use only.

TABLE 3-1:

PIN FUNCTION (CONTINUED)

HV7358

Symbol

Description

HV7358 Datasheet(PDF) 21 Page - Microchip Technology

HV7358 Datasheet(HTML) 21 Page - Microchip Technology

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50

Datasheet Download

Link URL