HV7358 datasheet(13/50 Pages) MICROCHIP

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 2018 Microchip Technology Inc.

DS20005918A-page 13

HV7358

TABLE 1-12:

SPI AND I2C I/O CHARACTERISTICS

Unless otherwise specified: VLL =+2.5V, AVDD =VDD =+5V, VPP =+80V, VNN =-80V, VGN = -5V, VSUB =0V, EN = 1,

TA =+25°C

Parameters

Sym.

Min.

Typ.

Max.

Units

Conditions

LVDS Differential Input: CLKP/N, SDIP/N, CSP/N and TRIGP/N Pins

SPI LVDS Clock I/O Frequency

fCLK

—

200

MHz

SPI LVDS Clock Input Duty Cycle(1)

AC Differential Sensitivity

VSNS

150

200

—

P-P at 200 MHz(1)

AC Common-Mode Voltage(1)

VCMAC

1—

1.4

DC Common-Mode Voltage

VREF

VLL/2 – 0.2 VLL/2

VLL/2 + 0.2

CLK Input Offset Voltage(1)

VOFFSET

—30

—

LVDS DC Input Differential Voltage

VID

100

350

600

Same as FPGA I/O

CLK Input Resistance

RIN_CLK

—5.0

—

kΩ

CLK Input Capacitance(2)

CIN_CLK

—4.0

—

CLK Input Bias Current

IBIAS_CLK

—

1.0

—

At input 200 mVp-p

LVDS Differential Output: CKOP/N, SDOP/N and CSOP/N Pins

LVDS DC Output Differential Voltage

VOD

300

500

—

RT =100Ω,

termination resistor

at the P to N LVDS

input pins(2)

LVDS DC Output Common-Mode

Voltage

VOCM

VLL/2 – 0.2 VLL/2

VLL/2 + 0.2

LVDS Output High Voltage for P&N Pins

VOH

—

1.38

1.6

LVDS Output Low Voltage for P&N Pins

VOL

0.9

1.03

—

Output Current for P&N Pins

IO_LVDS

±3.0

±3.5

±5.0

Output Rise Time

tRO

—1.5

—

Output Fall Time

tFO

—1.5

—

CKOP/N Output Clock Duty Cycle

D%CKO

49.5

50.5

At 200 MHz(2)

Output Rise Propagation Delay

tDRO

—

1.5

2.0

CKOP 50% to CKN

50%(2)

Output Fall Propagation Delay

tDFO

—1.5

2.0

BEN Enable Time

tBEN

—

0.7

1.0

BEN 50% to CLK

CKO, SDO and CSO Logic High

VOHO

1.95

—

CKO, SDO and CSO Logic Low

VOLO

——

0.35

Note 1:

Characterized only; not 100% tested in production.

Design guidance only.

A device must internally provide a hold time of at least 300 ns for the SDA signal (referred to as the VIHmin

of the SCL signal) in order to bridge the undefined region of the falling edge of SCL.

The maximum tHD,DAT only has to be met if the device does not stretch the LOW period (tLOW) of the SCL

signal.

A Fast mode I2C bus device can be used in a Standard mode I2C bus system, but the requirement of a

tSU,DAT of 250 ns must then be met. This will automatically be the case if the device does not stretch the

LOW period of the SCL signal. If such a device does stretch the LOW period of the SCL signal, it must out-

put the next data bit to the SDA line, tRmax +tSU,DAT = 1000 + 250 = 1250 ns (according to the Standard

mode I2C bus specification), before the SCL line is released.

The maximum tF for the SDA and SCL bus lines of 300 ns is longer than the specified maximum tof for the

output stages, 250 ns. This allows series protection resistors (Rs) to be connected between the SDA/SCL

pins and the SDA/SCL bus lines.

I/O pins of Fast mode devices must not obstruct the SDA and SCL lines if VLL is switched off.

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