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HV7358 Datasheet(PDF) 3 Page - Microchip Technology |
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HV7358 Datasheet(HTML) 3 Page - Microchip Technology |
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3 / 50 page  2018 Microchip Technology Inc. DS20005918A-page 3 HV7358 Functional Block Diagram V DD V DD 2 µF RDCP R PP TRIG Ch0 DLY0[11:0] 12-Bit B-Delay CW-Phase TLP0[6:0] 7-Bit Local PWM t OFF_P Counter TLN0[6:0] 7-Bit Local PWM t OFF_N Counter EOT0 CH0 Logic and Gate Driver TX0 X0 RX0 RX0 R GND V NF V PP V PF VNN V NEG PVDD RTZSW0 Rb TRSW0 RxDMP0 Rb R GND CKON CKOP OTPN ETO SPIB SLEEP DISC Overtemp and UVLO LPWM CLKP CLKN SDIN SDIP W[1:0] LPWM CW INV TCKP TCKN A2 A1 PEN LCKD A GND V SUB 2 µF GND VNN SUB -3 to -80V V NN 1 µF 100V CNF 2 µF V NF V DD LR V NF DISC V NF LR V NEG +2.5V 0.22 µF 2 µF +3 to +80V 2 µF 1 µF 100V V PF V GN V PP LR V PF I2C PLL TX15 X15 RX0 RX15 R GND V PP CPF AV DD 2 µF +5V V LL SCL SDA TGP0[6:0] 7-Bit t OFF_P Register SPI Global Wave Pattern and Launch Parameter Registers RPC0[7:0] 8-Bit Repeat Counter SPI 12-Bit or 26-Bit Beamform Fast Shift Registers V NEG C PLL SPIBC SPISEL V PF CSOP CSON CSN CSP PSEL PLLEN 0 1 I2C-ADJ SDOP SDON RDCN f C V NF V PP V PF VNN V NEG PV DD RTZSW15 Rb TRSW15 RxDMP15 Rb R GND BFEN 0 1 0 1 1 0 0 1 1 0 DQ DQ TGN0[6:0] 7-Bit t OFF_N Register TGW0[8:0] 9-Bit t Pulse_Width Register f T EN EOT[15:0] TRIG Ch15 CH15 Logic and Gate Driver RSTN BSEL BEN TXRW TGP1[6:0] 7-Bit t OFF_P Register RPC1[7:0] 8-Bit Repeat Counter TGN1[6:0] 7-Bit t OFF_N Register TGW1[8:0] 9-Bit t Pulse_Width Register TGP2[6:0] 7-Bit t OFF_P Register RPC2[7:0] 8-Bit Repeat Counter TGN2[6:0] 7-Bit t OFF_N Register TGW2[8:0] 9-Bit t Pulse_Width Register TGP3[6:0] 7-Bit t OFF_P Register RPC3[7:0] 8-Bit Repeat Counter TGN3[6:0] 7-Bit t OFF_N Register TGW3[8:0] 9-Bit t Pulse_Width Register DLY1[11:0] 12-Bit B-Delay CW-Phase TLP1[6:0] 7-Bit Local PWM t OFF_P Counter TLN1[6:0] 7-Bit Local PWM t OFF_N Counter DLY15[11:0] 12-Bit B-Delay CW-Phase TLP15[6:0] 7-Bit Local PWM t OFF_P Counter TLN15[6:0] 7-Bit Local PWM t OFF_N Counter f REF PFD f IN Ch1 A0 RD Back f CW0 CWFD[7:0] CWFD15[7:0] CW Frequency Divider Counter EOT15 f CW1 f CW15 f RT f RT SDLY 12/26 Cntrl Bits I2C-ADJ TRIG 16-Channel Beamform Registers f C f C f C Digital Lock Detector CW CWFD1[7:0] CW Frequency Divider Counter CWFD0[7:0] CW Frequency Divider Counter -5V (B and CW) or 0V (B only) 0.1 µF GND V PLL LR V PLL AV DD V NN V GN CNEG 2 µF V GN TRIGP TRIGN TRIG Loop Gain Filter ÷N VCO f VCO f VCO Buff EN TRIG OPT UVLO DNC FCEN (FC) +5V BEN EN Reg. Reset Q D C f C (Start TRSW on delay) EOTin ETI PV DD PV DD 2 µF +5V 0 1 EOTC GND |
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