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HV7358 Datasheet(PDF) 24 Page - Microchip Technology |
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HV7358 Datasheet(HTML) 24 Page - Microchip Technology |
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24 / 50 page ![]() HV7358 DS20005918A-page 24 2018 Microchip Technology Inc. 4.4.1 BROADCASTING vs. DAISY-CHAIN MODE The fast programming interface can also operate in two modes: Broadcasting mode or Daisy-Chain mode. The pin, SPIB, selects the operating mode. When the SPIB pin is high, the SPI interface operates in Broadcasting mode. When SPIB = 0, it operates in Daisy-Chain mode. Alternatively, the operating mode can be selected via the SPIBC bit in the I2C register, to control the SPI mode, if the override bit, SPISEL = 1. In Daisy-Chain mode, the LVDS output SDO is the Shift register output. SDO is the fast SPI Shift register out- put, which is either the 12-bit Delay register DLY[11:0] or 26-bit DLY[11:0], TLP[6:0] and TLN[6:0], depending on the SDLY selection. Data is clocked out of the Trans- mit Pattern Shift register onto SDO on the rising edge of the CKOP. In Broadcasting mode (pin SPIB = 1), the LVDS outputs, CSOP/CSON and SDOP/SDON, are matched in delay with the CKOP/CLON in timing, as shown in Figure 4-16. The Broadcasting mode should be used when all devices need to be programmed with the same data. In the medical ultrasound application, all the transmit channels have the same transmit patterns. In that scenario, the Broadcasting mode should be used to reduce the programming time. The Daisy-Chain mode should be used when the programming data is different across devices. In most medical ultrasound applica- tions, the transmit delay is different from channel to channel. In that scenario, the Daisy-Chain mode should be used when programming the channel delay counters. Note that the programming clocks, CLKP/N, are only used for programming the transmit patterns and the channel delay counters. The CLKP/N do not need to be active all the time and they can be turned off after SPI writing. FIGURE 4-2: Connection Circuit Block Diagram of Fast SPI Interface. HV7358 U2 U4 LVDS SDI TXRW Shift Reg. SPIB D0 Qn CLK CS SDO CSO TXRW CLK CS SDI FPGA SDO U1 HV7358 HV7358 SPIB SDI TXRW Shift Reg. SPIB D0 Qn CLK CS SDO CSO LVDS SDI TXRW Shift Reg. SPIB D0 Qn CLK CS SDO CSO CKO CKO CKO |
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