HV7358 datasheet(10/50 Pages) MICROCHIP

10 / 50 page

HV7358

DS20005918A-page 10

 2018 Microchip Technology Inc.

TABLE 1-9:

LOGIC INPUTS CHARACTERISTICS

TABLE 1-7:

TRSW AND RXDMP SWITCHES

Parameters

Sym.

Min.

Typ.

Max.

Units

Conditions

TRSW Analog Switch-On Resistor

RTRSW

—17

Ω

ITRSW =±1mA(1)

TRSW Off Withstand Voltage

VTRSW

-80

—

+80

ISW = ±100 μA(1)

RXCH to GND Protection Diode

—

±0.8

±1.2

IF =±20 mA(1)

RXDMP Switch-On Resistance

RRXDMP

—15

—

Ω

ISD =±1 mA(1)

RXCH Bleed Resistor to GND(1)

—17

—

kΩ

RXCH Pin to GND Capacitance

CRXG

—

7.0

At 1 MHz, 1 dBm, 0V DC(2)

Note 1:

Characterized only; not 100% tested in production.

Design guidance only.

TABLE 1-8:

BUILT-IN VOLTAGE LINEAR REGULATORS

Unless otherwise specified: VLL =+2.5V, AVDD =VDD =+5V, VPP = +80V, VNN =-80V, VGN =-5V, VSUB =0V, EN = 1,

PEN = BEN = 0, TA =+25°C

Parameters

Sym.

Min.

Typ.

Max.

Units

Conditions

Output P-Channel Gate Drive

Voltage Referenced to VPP

VPF

-4.9

-5.0

-5.1

(VGN –VPP)< -8.0V

Output N-Channel Gate Drive

Voltage Referenced to VNN

VNF

5.1

5.0

5.3

(VDD –VNN)> +8.0V

Output P-Channel Gate Drive

Voltage Referenced to GND

VNEG

-5.1

-5.0

-4.9

CW = 0

Output PLL Voltage Referenced to

GND

VPLL

4.4

4.6

4.8

PEN = 1

Dropout Voltage of (VPP –VGN)

VDOPF

—

3.5

—

100 mA load, drop to 95% at

worst case(1)

Dropout Voltage of (VDD –VNN)VDONF

—3.5

—

Dropout Voltage of (VNEG –VNN)VDONEG

—

1.36

—

10 mA load, drop to 95% at worst

case(1)

Dropout Voltage of (AVDD –VPLL)VDOPLL

—

0.31

—

1 mA load, drop to 95% at worst

case(1)

Note 1:

Characterized only; not 100% tested in production.

Parameters

Sym.

Min.

Typ.

Max.

Units

Conditions

Rise/Fall Time of Input Logic Signals

trf

—

3.5

10% to 90% at pin(s)(2)

Input Logic Low Voltage(1)

VIL

0—

0.2 VLL

Input Logic High Voltage(1)

VIH

0.8

—

VLL

Input Logic Low Current

IIL

-0.1

—

μA

Input Logic High Current

IIH

——

1.0

μA

Input Capacitance(2)

CIN

—2.0

3.0

EN Switching On Time

tEN

—300

—

μs

50% EN rise to TXCH ready(2)

EN Switching Off Time

—

300

—

50% EN fall to TXCH, all output

FETs on HV rails are off(1)

Internal Reset Signal Width(2)

tRST

100

—

150

Reset Input Low Time(1)

tRSTN

100

—

Note 1:

Characterized only; not 100% tested in production.

Design guidance only.

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