7.5 Programming

7.5.1 I2C and SMBus Interface

7.5.1.1 Serial Interface

The TMP118 has a standard bidirectional I2C interface that is controlled by a controller device. Each target on

the I2C bus has a specific device address to differentiate between other target devices that are on the same I2C

bus. Many target devices require configuration upon start-up to set the behavior of the device. This is typically

done when the controller accesses internal register maps of the target, which have unique register pointers. The

TMP118 supports transmission data rates up to 1MHz.

7.5.1.1.1 Bus Overview

The physical I2C interface consists of the serial clock (SCL) and serial data (SDA) lines. Both SDA and SCL lines

must be connected to a supply through an external pullup resistor (unless integrated within the controller). The

size of the pullup resistor is determined by the amount of capacitance on the I2C lines, the pullup bus voltage,

and the communication frequency. For further details, see the I2C Pullup Resistor Calculation application note.

Data transfer can be initiated only when the bus is idle. A bus is considered idle if both SDA and SCL lines are

high after a STOP condition.

I2C communication with this device is initiated by the controller sending a START condition and terminated by

the controller sending a STOP condition. A high-to-low transition on the SDA line while the SCL is high defines a

START condition. A low-to-high transition on the SDA line while the SCL is high defines a STOP condition.

A repeated START condition is similar to a START condition and is used in place of a back-to-back STOP then

START condition. A repeated START condition looks identical to a START condition, but differs from a START

condition because the condition occurs without a STOP condition (when the bus is not idle).

SCL

SDA

Data Transfer

START

Condition

STOP

Condition

Figure 7-9. Definition of Start and Stop Conditions

One data bit is transferred during each clock pulse of the SCL. One byte is comprised of eight bits on the

SDA line. A byte can either be a device address, register pointer, or data written to or read from a target. Data

is transferred Most Significant Bit (MSB) first. 2 bytes of data can be transferred from the controller to target

between the START and STOP conditions. Data on the SDA line must remain stable during the high phase of

the clock period, as changes in the data line when the SCL is high are interpreted as control commands (START

or STOP).

TMP118

SNIS237 – DECEMBER 2024

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