Byte: 1010 1010 (AAh)

MSB

SCL

SDA

Bit

Bit

Bit

Bit

Bit

Bit

LSB

ACK

1

0

1

0

1

0

1

0

ACK

SDA line is stable while SCL line is high

Figure 7-10. One Byte of Data Transfer

7.5.1.1.2 Device Address

To communicate with the TMP118 , the controller must first address target devices through an address byte. The

address byte has seven address bits and a read-write (R/W) bit that indicates the intent of executing a read or

write operation. The TMP118 utilizes hardwired orderables for addressing to allow up to 4 target devices to be

addressed on a single bus.

Table 7-4. Device Address Options

7-BIT I2C TARGET ADDRESS

DEVICE

HEX

BINARY

TMP118A/ TMP118MA

0x48

1001000'b

TMP118B/ TMP118MB

0x49

1001001'b

TMP118C/ TMP118MC

0x4A

1001010'b

TMP118D/ TMP118MD

0x4B

1001011'b

7.5.1.1.3 Writing and Reading Operation

7.5.1.1.3.1 Writes

To write on the I2C bus, the controller sends a START condition on the bus with the address of the target, as

well as the last bit (the R/W bit) set to 0b, which signifies a write. The target acknowledges, letting the controller

know the target is present on the bus and ready. After this, the controller starts sending the register pointer and

register data to the target until the controller has sent all the data necessary, and the controller terminates the

transmission with a STOP condition.

Writes to read-only registers or register locations outside of the register map are ignored. The TMP118 still

acknowledges (ACK) when writing outside of the register map. Figure 7-11 shows an example of writing 2-byte

data to a single register.

www.ti.com

TMP118

SNIS237 – DECEMBER 2024

Copyright © 2024 Texas Instruments Incorporated

Submit Document Feedback

21

Product Folder Links: TMP118