TAS3204 datasheet(16/72 Pages) TI

16 / 72 page

www.ti.com

3.10.3 2-Channel Right-Justified Timing

SCLK

32 Clks

LRCLK

Left Channel

24-Bit Mode

20-Bit Mode

16-Bit Mode

MSB

LSB

2-Channel Right-Justified (Sony Format) Stereo Input

32 Clks

Right Channel

MSB

LSB

T0034-03

3.10.4 SAP Input to SAP Output—Processing Flow

TAS3204

AUDIO DSP

WITH ANALOG INTERFACE

SLES197 – APRIL 2007

In 2-channel right-justified (RJ) timing, LRCLK is HIGH when left-channel data is transmitted and LOW

when right-channel data is transmitted. SCLK is a bit clock running at 64

× f

S which clocks in each bit of

the data. The first bit of data appears on the data lines 8 bit-clock periods (for 24-bit data) after LRCLK

toggles. In the RJ mode, the last bit clock before LRCLK transitions always clocks the LSB of data. The

data is written MSB first and is valid on the rising edge of the bit clock. The TAS3204 masks unused

leading data-bit positions.

Figure 3-4. Right-Justified 64fS Format

All SAP data format options other than I2S result in a two-sample delay from input to output. If I2S

formatting is used for both the input SAP and the output SAP, the polarity of LRCLK must be inverted.

However, if I2S format conversions are performed between input and output, the delay becomes either 1.5

samples or 2.5 samples, depending on the processing clock frequency selected for the audio DSP core

relative to the sample rate of the incoming data.

The I2S format uses the falling edge of LRCLK to begin a sample period, whereas all other formats use

the rising edge of LRCLK to begin a sample period. This means that the input SAP and audio DSP core

operate on sample windows that are 180

° out of phase with respect to the sample window used by the

output SAP. This phase difference results in the output SAP outputting a new data sample at the midpoint

of the sample period used by the audio DSP core to process the data. If the processing cycle completes

all processing tasks before the midpoint of the processing sample period, the output SAP outputs this

processed data. However, if the processing time extends past the midpoint of the processing sample

period, the output SAP outputs the data processed during the previous processing sample period. In the

former case, the delay from input to output is 1.5 samples. In the latter case, the delay from input to output

is 2.5 samples.

Physical Characteristics

Submit Documentation Feedback

TAS3204 Datasheet(PDF) 16 Page - Texas Instruments

TAS3204 Datasheet(HTML) 16 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72

Datasheet Download

Link URL