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TAS3204 Datasheet(PDF) 3 Page - Texas Instruments

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Part # TAS3204
Description  AUDIO DSP WITH ANALOG INTERFACE
PDF  72 Pages
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Manufacturer  TI [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI - Texas Instruments

TAS3204 Datasheet(HTML) 3 Page - Texas Instruments

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Functional Description
DSP Core
8051MicroprocessorCore
Oscillator
DPLL
Clock
Divider
512FsXTAL
MCLK_IN
512Fs
Slave
Clock
Generation
Serial AudioPort
LRCLK_OUT
SCLK_OUT
LRCLK_IN
SCLK_IN
SDOUT1/2
TwoStereo
ADC
Three
Differential
Stereo
AnalogInputs
TwoStereo
DAC
TwoDifferential
Stereo Analog
Outputs
SCL1/SDA1
SCL2/SDA2
GPIO1/2
Master/Slave
Power
Supply
AVDD
DVDD
128Fs
Volume
Update
Input
Cross
Bar
Mixer
OutputCross
BarMixer
SDIN1/2
Clocks
Legend
DigitalData
AnalogData
InternalConnection
External Connection
Control
Registers
External
RAM2K
Code
RAM16K
8-Bit
MCU
Internal
RAM256
DataRAM
1KUpperMem
768LowerMem
Coefficient
RAM 1.2K
Code
RAM 3K
DSP
Control
Memory
Interface
Data
Path
I2C
Control
Interface
TAS3204
AUDIO DSP
WITH ANALOG INTERFACE
SLES197 – APRIL 2007
The TAS3204 is an audio system-on-a-chip (SOC) designed for mini/micro systems, multimedia-speaker,
and MP3 player docking systems. It includes analog interface functions: three multiplex (MUX) stereo
inputs with two stereo analog-to-digital converters (ADCs), two stereo digital-to-analog converters (DACs)
with analog outputs consisting of differential stereo line drivers. Four channels of serial digital audio
processing are also provided. The TAS3204 has a programmable audio digital signal processor (DSP) that
preserves high-quality audio by using a 48-bit data path, 28-bit filter coefficients, and a single cycle
28
×48-bit multiplier. The programmability feature allows users to customize features in the DSP RAM.
The TAS3204 is composed of eight functional blocks:
1. Analog input/mux/stereo ADC
2. Two stereo DACs
3. Analog reference system
4. Power supply
5. Clocks, digital pll, and serial data interface
6. I2C control interface
7. 8051 microcontroller
8. Audio DSP – digital audio processing
Figure 2-1. Expanded Functional Block Diagram
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Functional Description
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