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TAS3204 Datasheet(PDF) 27 Page - Texas Instruments |
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TAS3204 Datasheet(HTML) 27 Page - Texas Instruments |
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27 / 72 page  www.ti.com 6.3.1 Multiple-Byte Write D7 D0 ACK Stop Condition Acknowledge I CDevice Addressand 2 Read/WriteBit Subaddress LastDataByte A6 A5 A1 A0 R/W ACK A7 A5 A1 A0 ACK D7 ACK Start Condition Acknowledge Acknowledge Acknowledge FirstDataByte A4 A3 A6 OtherDataBytes ACK Acknowledge D0 D7 D0 T0036-02 6.3.2 Multiple-Byte Read A6 A0 ACK Acknowledge I CDevice Addressand Read/WriteBit 2 R/W A6 A0 R/W ACK A0 ACK D7 D0 ACK Start Condition Stop Condition Acknowledge Acknowledge Acknowledge LastDataByte ACK FirstDataByte RepeatStart Condition Not Acknowledge I CDevice Addressand Read/WriteBit 2 Subaddress OtherDataBytes A7 A6 A5 D7 D0 ACK Acknowledge D7 D0 T0036-04 6.4 I2C Master-Mode Device Initialization TAS3204 AUDIO DSP WITH ANALOG INTERFACE SLES197 – APRIL 2007 If the master device issues more data-received acknowledges than required to receive the data for a given subaddress, the master device simply receives complete or partial sets of data, depending on how many data-received acknowledges are issued from the subaddress(es) that follow. I2C read transactions, both sequential and random, can impose wait states. Multiple data bytes are transmitted by the master device to slave as shown in Figure 6-4. After receiving each data byte, the TAS3204 responds with an acknowledge bit. Figure 6-4. Multiple-Byte Write Transfer Multiple data bytes are transmitted by the TAS3204 to the master device as shown in Figure 6-5. Except for the last data byte, the master device responds with an acknowledge bit after receiving each data byte. Figure 6-5. Multiple-Byte Read Transfer I2C master-mode operation is enabled following a reset or power-on reset. Master-mode I2C transactions do not start until the I2C bus is idle. The TAS3204 uses the master mode to download from EEPROM the memory contents for the microprocessor program memory, microprocessor extended memory, audio DSP core program memory, audio DSP core coefficient memory, and audio DSP core data memory. The TAS3204, when operating as an I2C master, can execute a complete download of any internal memory or any section of any internal memory without requiring any wait states. When the TAS3204 operates as an I2C master, the TAS3204 generates a repeated start without an intervening stop command while downloading program and memory data from EEPROM. When a repeated start is sent to the EEPROM in read mode, the EEPROM enters a sequential read mode to transfer large blocks of data quickly. The TAS3204 queries the bus for an I2C EEPROM at address 1010xxx. The value xxx can be chip select, other information, or don’t cares, depending on the EEPROM selected. Submit Documentation Feedback Microprocessor Controller 27 |
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