TAS3204 datasheet(21/72 Pages) TI

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Microprocessor Controller

TAS3204

AUDIO DSP

WITH ANALOG INTERFACE

SLES197 – APRIL 2007

The 8051 microprocessor receives and distributes I2C write data, retrieves and outputs to the I2C bus

controllers the required I2C read data, and participates in most processing tasks requiring multiframe

processing cycles. The microprocessor has its own data RAM for storing intermediate values and queuing

I2C commands, a fixed boot-program ROM, and a program RAM. The microprocessor boot program

cannot be altered. The microprocessor controller has specialized hardware for master and slave interface

operation, volume updates, and a programmable interval timer interrupt. For more information see the

TAS3108/TAS3108IA Firmware Programmer's Guide (SLEU067).

The TAS3204 has a slave-only I2C interface that is compatible with the Inter IC (I2C) bus protocol and

supports both 100-kbps and 400-kbps data-transfer rates for multiple 4-byte write and read operations

(maximum is 20 bytes). The slave I2C control interface is used to program the registers of the device and

to read device status.

The TAS3204 also has a master-only I2C interface that is compatible with the I2C bus protocol and

supports 375-kbps data transfer rates for multiple 4-byte write and read operations (maximum is 20 bytes).

The master I2C interface is used to load program and data from an external I2C EEPROM.

On power up of the TAS3204, the slave interface is disabled and the master interface is enabled.

Following a reset, the TAS3204 disables the slave interface and enables the master interface. Using the

master interface, the TAS3204 automatically tests to see if an I2C EEPROM is at address 1010x. The

value x can be chip select, other information, or don’t cares, depending on the EEPROM selected. If a

memory is present and it contains the correct header information and one or more blocks of

program/memory data, the TAS3204 loads the program, coefficient, and/or data memories from the

EEPROM. If a memory is present, the download is complete when a header is read that has a zero-length

data segment. At this point, the TAS3204 disables the master I2C interface, enables the slave I2C

interface, and starts normal operation.

If no memory is present or if an error occurred during the EEPROM read, TAS3204 disables the master

I2C interface, enables the slave I2C interface, and loads the unprogrammed default configuration. In this

default configuration, the TAS3204 streams audio from input to output if the GPIO pin is LOW. The master

and slave interfaces do not operate simultaneously.

In the slave mode, the I2C bus is used to:

• Load the program and coefficient data

–

Microprocessor program memory

–

Microprocessor extended memory

–

Audio DSP core program memory

–

Audio DSP core coefficient memory

–

Audio DSP core data memory

• Update coefficient and other control values

• Read status flags

Once the microprocessor program memory has been loaded, it cannot be updated until the TAS3204 has

been reset.

The master and slave modes do not operate simultaneously.

When acting as an I2C master, the data transfer rate is fixed at 375 kHz, assuming MCLK_IN or

XTAL_IN = 24.576 MHz.

When acting as an I2C slave, the data transfer rate is determined by the master device on the bus.

The I2C communication protocol for the I2C slave mode is shown in Figure 6-1.

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Microprocessor Controller

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