TAS3204 datasheet(2/72 Pages) TI

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Contents

TAS3204

AUDIO DSP

WITH ANALOG INTERFACE

SLES197 – APRIL 2007

Introduction

............................................... 1

8.1

Absolute Maximum Ratings

......................... 37

1.1

Features

.............................................. 1

8.2

Package Dissipation Ratings

........................ 37

1.2

Applications

........................................... 1

8.3

Recommended Operating Conditions

............... 37

Functional Description

................................. 3

8.4

Electrical Characteristics

............................ 38

2.1

Analog Input/MUX/Stereo ADCs

..................... 4

8.5

Audio Specifications

................................. 38

2.2

Stereo DACs

.......................................... 4

8.6

Timing Characteristics

............................... 41

2.3

Analog Reference System

............................ 4

8.6.1

Master Clock

....................................... 41

2.4

Power Supply

......................................... 4

8.6.2

Serial Audio Port, Slave Mode

..................... 42

8.6.3

Serial Audio Port Master Mode Signals

2.5

Clocks, Digital PLL, and Serial Data Interface

....... 4

(TAS3204)

........................................... 43

2.6

I2C Control Interface

.................................. 6

8.6.4

Pin-Related Characteristics of the SDA and SCL

2.7

8051 Microcontroller

................................. 6

I/O Stages for F/S-Mode I2C-Bus Devices

.......... 44

2.8

Audio Digital Signal Processor Core

................. 6

8.6.6

Reset Timing

........................................ 46

Physical Characteristics

............................... 7

I2C Register Map

........................................ 47

3.1

Terminal Assignments

................................ 7

9.1

Clock Control Register (0x00)

...................... 48

3.2

Ordering Information

.................................. 7

9.2

Microcontroller Clock Control Register

.............. 48

3.3

Terminal Descriptions

................................ 8

9.3

Status Register (0x02)

.............................. 49

3.4

Reset (RESET) - Power-Up Sequence

............. 10

9.4

I2C Memory Load Control and Data Registers (0x04

3.5

Voltage Regulator Enable (VREG_EN)

............. 10

and 0x05)

............................................ 50

3.6

Power-On Reset (RESET)

.......................... 10

9.5

Memory Access Registers (0x06 and 0x07)

........ 51

3.7

Power Down (PDN)

................................. 10

9.6

Device Version (0x08)

............................... 52

3.8

I2C Bus Control (CS0)

............................... 11

9.7

Analog Power Down Control (0x10 and 0x11),

ESFR (0xE1 and 0xE2)

............................. 52

3.9

Programmable I/O (GPIO)

.......................... 11

9.8

Analog Input Control (0x12), ESFR (0xE3)

......... 53

3.10

Input and Output Serial Audio Ports

................ 12

9.9

Dynamic Element Matching (0x13), ESFR (0XE4)

.. 53

Algorithm and Software Development Tools for

TAS3204

.................................................. 18

9.10

Current Control Select (0x14, 0x15, 0x17, 0x18),

ESFR (0xE5, 0xE6, 0xE7, 0xE9)

.................... 54

Clock Controls

.......................................... 19

9.11

DAC Control (0x1A, 0x1B, 0x1D), ESFR (0xEB,

Microprocessor Controller

.......................... 21

0xEC, 0xEE)

......................................... 58

6.1

8051 Microprocessor Addressing Mode

............ 22

9.12

ADC and DAC Reset (0x1E), ESFR (0xFB)

........ 60

6.2

General I2C Operations

............................. 23

9.13

ADC Input Gain Control (0x1F), ESFR (0xFA)

...... 60

6.3

I2C Slave Mode Operation

.......................... 24

9.14

MCLK_OUT Divider (0x21 and 0x22)

............... 61

6.4

I2C Master-Mode Device Initialization

.............. 27

9.15

Digital Cross Bar (0x30 to 0x3F)

.................... 61

Digital Audio Processor (DAP) Arithmetic Unit

. 33

9.16

Extended Special Function Registers (ESFR) Map

. 63

7.1

DAP Instructions Set

................................ 34

Application Information

............................... 68

7.2

DAP Data Word Structure

........................... 35

10.1

Schematics

.......................................... 68

Electrical Specifications

.............................. 37

10.2

Recommended Oscillator Circuit

.................... 69

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