WM8805 datasheet(55/65 Pages) WOLFSON

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Production Data

WM8805

PD Rev 4.1 September 07

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

1:0

MODE[1:0]

PLL Post-scale Divider Select

Selects the PLL output divider value in

conjunction with MCLKDIV and CLKOUTDIV.

Refer to Table 23 for details of FREQMODE

operation.

Note: FREQMODE[1:0] bits are

automatically set in S/PDIF Receive Mode.

FRACEN

Integer/Fractional PLL Mode Select

0 = Integer PLL (PLL_N value used, PLL_K

value ignored)

1 = Fractional PLL (both PLL_N and PLL_K

values used)

Note: FRACEN must be set to enable the

fractional PLL when using S/PDIF Receive

Mode.

MCLKDIV

MCLK Divider Select

(Only valid when CLK2 is selected as MCLK

output source)

See Table 23 for MCLKDIV configuration in

PLL user mode.

See Table 28 for MCLKDIV configuration in

PLL S/PDIF receive mode.

PLL5

07h

5:4

CLKOUTDIV[1:0]

CLKOUT Divider Select

(Only valid when CLK1 is selected as CLKOUT

output source)

See Table 27 for CLKOUTDIV[1:0]

configuration in PLL user mode.

See Table 28 for CLKOUTDIV[1:0]

configuration in PLL S/PDIF receive mode.

WM8805 Datasheet(PDF) 55 Page - Wolfson Microelectronics plc

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