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POWER MANAGEMENT

SC480

POWER MANAGEMENT

Thermal Considerations

The junction temperature of the device may be calculated

as follows:

J = TAMB + θJA

where T

J is the junction temperature, TAMB is the ambient

temperature, PD is the total SC480 device dissipation,

The SC480 device dissipation can be determined using:

PD = VCCA • ICCA + VDDP • IDDP + VTT • |ITT|

The ﬁrst two terms are losses for the analog and gate drive

circuits and generally do not present a thermal problem.

Typical ICCA (VCCA operating current) is roughly 1.5mA,

which creates 7.5mW loss from the 5V VCCA supply. The

VDDP supply current is used to drive the MOSFETs and

can be much higher, on the order of 30mA, which can

create up to 150mW of dissipation.

The last term, VTT * |ITT|, is the most signiﬁcant term

from a thermal standpoint. The VTT regulator is a linear

device and will dissipate power proportional to the VTT

current and the voltage drop across the regulator. If VTT

= VDDQ/2, then the voltage drop across the regulator

is always VDDQ2, regardless of whether the regulator is

sinking or sourcing current. In either case the power lost

in the VTT regulator is VTT * |ITT|. The average or long-

term value for ITT should be used.

The thermal resistance of the MLPQ package is affected

by PCB layout and the available ground planes and vias

which conduct heat away. A typical value is 29°C/watt.

Example:

ICCA = 1.5mA

IDDP = 25mA

VCCA = VDDP = 5V

VTT = 1.25V

ITT = 0.75A (average)

Ambient = 45 degrees C

Thermal resistance = 29

D = 5V • 0.0015 A + 5V • 0.025A + 0.9V • |0.75|A

D = 0.808W

J = TAMB + PD • TJA = 45 + 0.808W • 29°C/W = 68.4°C

Application Information (Cont.)

Layout Guidelines

One (or more) ground planes are recommended to

minimize the effect of switching noise and copper losses,

and maximize heat dissipation. The IC ground reference,

VSSA, should be connected to PGND1 and PGND2 as a

star connection at the thermal pad, which in connects

using 4 vias to the ground plane. All components that are

referenced to VSSA should connect to it directly on the

chip side, and not through the ground plane.

VDDQ: The feedback trace must be kept far away from

noise sources such as switching nodes, inductors and

gate drives. Route the feedback trace in a quiet layer if

possible, from the output capacitor back to the chip. Chip

supply decoupling capacitors (VCCA, VDDP) should be

located next to the pins (VCCA/VSSA, VDDP/PGND1) and

connected directly to them on the same side.

VTT: Because of the high bandwidth of the VTT regulator,

proper component placement and routing is essential to

prevent unwanted high-frequency oscillations which can

be caused by parasitic inductance and noise. The input

capacitors should be located at the VTT input pins (VTTIN

and PGND2), as close as possible to the chip to minimize

parasitics. Output capacitors should be directly located at

the VTT output pins (VTT and PGND2). The routing of the

feedback signal VTTS is critical. The trace from VTTS (pin

2) should be connected directly to the output capacitor

that is farthest from VTT (pin24); route this signal away

from noise sources such as the VDDQ power train or high-

speed digital signals.

The switcher power section should connect directly to the

ground plane(s) using multiple vias as required for current

handling (including the chip power ground connections).

Power components should be placed to minimize loops

and reduce losses. Make all the connections on one side

of the PCB using wide copper ﬁlled areas if possible. Do

not use “minimum” land patterns for power components.

Minimize trace lengths between the gate drivers and the

gates of the MOSFETs to reduce parasitic impedances

(and MOSFET switching losses); the low-side MOSFET is

most critical. Maintain a length to width ratio of <20:1 for

gate drive signals. Use multiple vias as required by current

handling requirement (and to reduce parasitics) if routed

on more than one layer. Current sense connections must

always be made using Kelvin connections to ensure an

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