CMOS Low Power Timer – LMC555

Rev 1.1

21/01/18

 

Application Notes Continued

 

 

f = 1.44 / (RA + 2RB) C

VDD

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

RA

GND

1

8

TRIGGER

CONTROL

THRESHOLD

DISCHARGE

2

7

3

4

6

5

Figure 4 – Astable Operation (Adjustable Duty Cyle) 

C

RB

OUTPUT

VDD

Optional

Capacitor

Duy Cycle is controlled by D = (RA + RB) / (RA + 2RB)

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