TMS320C6421 datasheet(103/223 Pages) TI

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TMS320C6421

Fixed-Point Digital Signal Processor

SPRS346C – JANUARY 2007 – REVISED NOVEMBER 2007

Table 3-37. EMIFA Block Major Configuration Choices

MAJOR

PINMUX SELECTION FIELDS

RESULTING PERIPHERALS/PINS

CONFIG.

AEM

RMII

CS3SEL

CS4SEL

CS5SEL

EMIFA

(1)

RMII

GPIO

OPTION

58 GP Pins:

000

GP[96:89], GP[54:5]

RMII:

50 GP Pins:

RMRXER, RMRXD[1:0],

000

GP[96:89], GP[54:53],

RMTXD[1:0], REFCLK,

GP[51:34], GP[26:5],

RMCRSDV, RMTXEN

8-bit EMIFA (Async) Pinout

Mode 2:

EM_A[21:0], EM_D[7:0],

13 GP pins:

EM_R/W, EM_CS2,

GP[54:52], GP[31:22]

EM_BA[1:0],

EM_WAIT/(RDY/BSY),

Optional Selection:

010

0 or 1

EM_WE, EM_OE

GP[33] (CS5SEL = 0),

GP[32] (CS4SEL = 0),

Optional Selection:

GP[13] (CS3SEL = 0)

EM_CS5 (CS5SEL = 1),

EM_CS4 (CS4SEL = 1),

EM_CS3 (CS3SEL = 1)

8-bit EMIFA (Async) Pinout

Mode 2:

EM_A[21:0], EM_D[7:0],

7 GP pins:

RMII:

EM_R/W, EM_CS2,

GP[54:53], GP[26:22]

RMRXER, RMRXD[1:0],

EM_BA[1:0],

010

0 or 1

RMTXD[1:0], REFCLK,

EM_WAIT/(RDY/BSY),

Optional Selection:

RMCRSDV, RMTXEN

EM_WE, EM_OE

GP[13] (CS3SEL = 0)

Optional Selection:

EM_CS3 (CS3SEL = 1)

8-bit EMIFA (NAND) Pinout

Mode 5:

44 GP pins:

EM_D[7:0], EM_A[2:1],

GP[96:89], GP[54:34],

EM_CS2,

GP[31:22], GP[11:10],

EM_WAIT/(RDY/BSY),

GP[7:5]

101

0 or 1

EM_WE, EM_OE

Optional Selection:

GP[33] (CS5SEL = 0),

EM_CS5 (CS5SEL = 1),

GP[32] (CS4SEL = 0),

EM_CS4 (CS4SEL = 1),

GP[13] (CS3SEL = 0)

EM_CS3 (CS3SEL = 1)

8-bit EMIFA (NAND) Pinout

Mode 5:

38 GP pins:

EM_D[7:0], EM_A[2:1],

GP[96:89], GP[54:34],

RMII:

EM_CS2,

GP[26:22], GP[11:10],

RMRXER, RMRXD[1:0],

101

0 or 1

EM_WAIT/(RDY/BSY),

GP[7:5]

RMTXD[1:0], REFCLK,

EM_WE, EM_OE

RMCRSDV, RMTXEN

Optional Selection:

GP[13] (CS3SEL = 0)

EM_CS3 (CS3SEL = 1)

(1)

The EMIFA pins EM_WAIT/(RDY/BSY), EM_OE, and EM_WE are non-multiplexed pins. They are available in all the configuration

options. However, they are only useful if additional EMIFA pins are functional. Therefore in this table, these pins are only listed in

configuration options C,D,E, and F.

The following is an example on how to read Table 3-37. For example, the "PINMUX Selection Fields"

columns indicate that Major Configuration Choice C is selected through setting PINMUX0.AEM = 010b

and PINMUX0.RMII = 0. Other PINMUX0 fields CS3SEL, CS4SEL, and CS5SEL can be set to either 0 or

1 based on the system's EMIFA Chip Select space need. The "Resulting Peripherals/Pins" columns

indicate that Major Configuration Option C can support the following combination of pin functions:

• Pins for 8-bit EMIFA (Async or NAND) function with EMIFA Chip Select space 2 (EM_CS2). If

additional Chip Select spaces are needed, set the corresponding PINMUX bit (CS5SEL, CS4SEL,

and/or CS3SEL) to 1.

• At least 13 GPIO pins. If the additional Chip Select spaces from EM_CS3, EM_CS4, or EM_CS5 are

not needed, the corresponding PINMUX bit (CS3SEL, CS4SEL, and/or CS5SEL) can be set to 0 to get

additional GPIO pins.

3.7.3.11.2 EMIFA Block Pin-By-Pin Multiplexing Summary

This section summarizes the EMIFA Block muxing on a pin-by-pin basis. It provides an alternative view to

pin muxing in the EMIFA Block. It summarizes the EMIFA Block pin muxing by dividing up the EMIFA

Block based on the PINMUX field that controls the pins. To determine the actual EMIFA Major

Configuration Option for the application need, see Section 3.7.3.11.1, EMIFA Block Major Configuration

Choices.

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