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ADV3000 Datasheet(PDF) 13 Page - Analog Devices

Part # ADV3000
Description  3:1 HDMI/DVI Switch with Equalization
PDF  28 Pages
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Manufacturer  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

ADV3000 Datasheet(HTML) 13 Page - Analog Devices

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ADV3000
Rev. 0 | Page 13 of 28
The ADV3000 requires output termination resistors when the
high speed outputs are enabled. Termination can be internal
and/or external. The internal terminations of the ADV3000
are enabled by programming the TX_PTO bit of the transmitter
settings register. These terminations are always enabled in
parallel control mode.
External terminations can be provided either by on-board
resistors or by the input termination resistors of an HDMI/
DVI receiver. If both the internal terminations are enabled and
external terminations are present, set the output current level to
20 mA by programming the TX_OCL bit of the transmitter
settings register through the serial control interface or by setting
the PP_OCL pin of the parallel control interface. The output
current level defaults to the level indicated by PP_OCL upon
reset. If only external terminations are provided (if the internal
terminations are disabled), set the output current level to 10 mA
by programming the TX_OCL bit of the transmitter settings
register or by setting the PP_OCL pin of the parallel control
interface. The high speed outputs must be disabled if there are
no output termination resistors present in the system.
The output pre-emphasis can be manually configured to provide
one of four different levels of high frequency boost. The specific
boost level is selected by programming the TX_PE bits of the
transmitter settings register through the serial control interface,
or by setting the PP_PE bus of the parallel control interface. No
specific cable length is suggested for a particular pre-emphasis
setting because cable performance varies widely between
manufacturers.
AUXILIARY SWITCH
The auxiliary (low speed) lines have no amplification. They are
routed using a passive switch that is bandwidth compatible with
standard speed I2C. The schematic equivalent for this passive
connection is shown in Figure 27.
AUX_COM0
AUX_A0
½CAUX
½CAUX
RAUX
Figure 27. Auxiliary Channel Simplified Schematic,
AUX_A0 to AUX_COM0 Routing Example
When turning off the ADV3000, care needs to be taken with
the AMUXVCC supply to ensure that the auxiliary multiplexer
pins remain in a high impedance state. A scenario that illustrates
this requirement is one where the auxiliary multiplexer is used
to switch the display data channel (DDC) bus. In some applica-
tions, additional devices can be connected to the DDC bus
(such as an EEPROM with EDID information) upstream of
the ADV3000. Extended display identification data (EDID)
is a VESA standard-defined data format for conveying display
configuration information to sources to optimize display use.
EDID devices may need to be available via the DDC bus, regard-
less of the state of the ADV3000 and any downstream circuit.
For this configuration, the auxiliary inputs of the powered
down ADV3000 need to be in a high impedance state to avoid
pulling down on the DDC lines and preventing these other
devices from using the bus.
When the ADV3000 is powered from a simple resistor network,
as shown in Figure 28, it uses the 5 V supply that is required
from any HDMI/DVI source to guarantee high impedance of
the auxiliary multiplexer pins. The AMUXVCC supply does not
draw any static current; therefore, it is recommended that the
resistor network tap the 5 V supplies as close to the connectors
as possible to avoid any additional voltage drop.
This precaution does not need to be taken if the DDC
peripheral circuitry is connected to the bus downstream of
the ADV3000.
PERIPHERAL
CIRCUITRY
+5V SOURCE C
PIN 18 HDMI CONNECTOR
PIN 14 DVI CONNECTOR
10kΩ
10MΩ
I<50mA
PERIPHERAL
CIRCUITRY
PERIPHERAL
CIRCUITRY
SOURCE A +5V
SOURCE B +5V
PIN 18 HDMI CONNECTOR
PIN 14 DVI CONNECTOR
PIN 18 HDMI CONNECTOR
PIN 14 DVI CONNECTOR
10kΩ
10kΩ
I<50mA
I<50mA
AMUXVCC
ADV3000
+5V INTERNAL
(IF ANY)
Figure 28. Suggested AMUXVCC Power Scheme



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