TMP88CS34FG datasheet(72/215 Pages) TOSHIBA

72 / 215 page

TMP88CS34/CP34

2007-09-12

88CS34-72

(2) Event counter mode

In this mode, events are counted on the rising edge of the TC2 pin input. The contents of

TC2DR are compared with the contents of the up-counter. If a match is found, an INTTC2

interrupt is generated, and the counter is cleared. The minimum pulse width to the TC2 pin

is shown in Table 2.6.2. Two or more machine cycles are required for both the “H” and “L”

levels of the pulse width. Match detect is executed on the falling edge of the TC2 pin. A

match can not be detected and INTTC2 is not generated when the pulse is still in a falling

state.

Example: Sets the event counter mode and generates an INTTC2 interrupt 640 counts

later.

LDW (TC2DR), 640

;

Sets TC2DR

SET

(EIRH). 6

;

Enables INTTC2 interrupt

(TC2CR), 00011100B

;

Selects TC2 source clock

(TC2CR), 00111100B

;

Starts TC2

Table 2.6.2 Timer/Counter 2 External Clock Source

Minimum pulse width [S]

NORMAL, IDLE mode

“H” width

3/fc

“L” width

3/fc

Figure 2.6.4 Event Counter Mode Timing Chart

Timer register

INTTC2 interrupt

TC2 pin input

Up-counter

Match detect

Counter clear

Count start

− 1

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