TMP88CS34FG datasheet(91/215 Pages) TOSHIBA

91 / 215 page

TMP88CS34/CP34

2007-09-12

88CS34-91

(1) Acknowledgement mode specification

a. Acknowledgement mode (ACK

= “1”)

To set the device as an acknowledgement mode, the ACK (bit4 in SBICRA) should be

set to “1”. When a serial bus interface circuit is a master mode, an additional clock

pulse is generated for an acknowledge signal. In a slave mode, a clock is counted for the

acknowledge signal.

In the master transmitter mode, the SDA pin is released in order to receive an

acknowledge signal from the receiver during additional clock pulse cycle. In the master

receiver mode, the SDA pin is set to low level generation an acknowledge signal during

additional clock pulse cycle.

In a slave mode, when a received slave address matches to a slave address which is

set to the I2CAR or when a “GENERAL CALL” is received, the SDA pin is set to low

level generating an acknowledge signal. After the matching of slave address or the

detection of “GENERAL CALL”, in the transmitter the SDA pin is released in order to

receive an acknowledge signal from the receiver during additional clock pulse cycle. In

a receiver, the SDA pin is set to low level generation an acknowledge signal during

additional clock pulse cycle after the matching of slave address or the detection of

“GENERAL CALL”.

The Table 2.9.1 shows the SCL and SDA pins status in acknowledgement mode.

Table 2.9.1 SCL and SDA Pins Status in Acknowledgement Mode

Mode

Transmitter

Receiver

SCL

An additional clock pulse is generated.

Master

SDA

Released in order to receive

and acknowledge signal.

Set to low level generating an

acknowledge signal.

SCL

A clock is counted for the acknowledge signal.

When slave address

matches or a general

call is detected

−

Set to low level generating an

acknowledge signal.

Slave

SDA

After matching of slave

address or general call

Released in order to receive

an acknowledge signal.

Set to low level generating an

acknowledge signal.

b. Non-acknowledgement mode (ACK

= “0”)

To set the device as a non-acknowledgement mode, the ACK should be cleared to “0”.

In the master mode, a clock pulse for an acknowledge signal is not generated. In the

slave mode, a clock for a acknowledge signal is not counted.

(2) Number of transfer bits

The BC (bits 7 to 5 in SBICRA) is used to select a number of bits for next transmitting

and receiving data.

Since the BC is cleared to “000” as a start condition, a slave address and direction bit

transmissions are always executed in 8 bits. Other than these, the BC retains a specified

value.

TMP88CS34FG Datasheet(PDF) 91 Page - Toshiba Semiconductor

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