TMP88CS34FG datasheet(17/215 Pages) TOSHIBA

17 / 215 page

TMP88CS34/CP34

2007-09-12

88CS34-17

STOP mode can also be released by setting the RESET pin low, which immediately

performs the normal reset operation.

Note:

When STOP mode is released with a low hold voltage, the following cautions must be

observed.

The power supply voltage must be at the operating voltage level before releasing STOP

mode. The RESET pin input must also be high, rising together with the power supply

voltage. In this case, if an external time constant circuit has been connected, the RESET

pin input voltage will increase at a slower rate than the power supply voltage. At this time,

there is a danger that a reset may occur if input voltage level of the RESET pin drops

below the non-inverting high-level input voltage (hysteresis input).

(2) IDLE mode

IDLE mode is controlled by the system control register 2 and maskable interrupts. The

following status is maintained during IDLE mode.

1. Operation of the CPU and watchdog timer is halted. On-chip peripherals continue to

operate.

2. The data memory, CPU registers and port output latches are all held in the status in

effect before IDLE mode was entered.

3. The program counter holds the address of the instruction following the instruction

which started IDLE mode.

Example: Starting IDLE mode.

SET

(SYSCR2) . 4

;

IDLE

← 1

Figure 1.4.12 IDLE Mode

Normal

release mode

Reset

Yes (Interrupt release mode)

Yes

No (high)

CPU, WDT are halted

Execution of the

instruction which follows

the IDLE mode start

instruction

Interrupt processing

IMF

= 1

Interrupt request

Reset input

Starting IDLE mode

by instruction

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