TMP88CS42FG datasheet(33/216 Pages) TOSHIBA

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Page 23

TMP88CS42FG

2.1.5 Reset Circuit

The TMP88CS42FG has four ways to generate a reset: external reset input, address trap reset, watchdog

timer reset, or system clock reset.

Table 2-3 shows how the internal hardware is initialized by reset operation.

At power-on time, the internal cause reset circuits (watchdog timer reset, address trap reset, and system clock

reset) are not initialized.

2.1.5.1 External Reset Input

The RESET pin is a hysteresis input with a pull-up resistor included. By holding the RESET pin low for

at least three machine cycles (12/fc [s]) or more while the power supply voltage is within the rated operat-

ing voltage range and the oscillator is oscillating stably, the device is reset and its internal state is initial-

ized.

When the RESET pin input is released back high, the device is freed from reset and starts executing the

program beginning with the vector address stored at addresses FFFFCH to FFFFEH.

Figure 2-12 Reset Circuit

2.1.5.2 Adress Trap Reset

If the CPU should start looping for reasons of noise, etc. and attempts to fetch instructions from the

internal RAM,SFR or DBR area, the device generats an internal reset.

The addess trap permission/prohibition is set by the address trap reset control register (ATAS,ATKEY).

The address trap is permited initially and the internal reset is generated by fetching from internal

RAM,SFR or DBR area. If the address trap is prohibited, instructions in the internal RAM area can be

executed.

Table 2-3 Internal Hardware Initialization by Reset Operation

Internal Hardware

Initial Value

Internal Hardware

Initial Value

Program Counter (PC)

(FFFFEH to FFFFCH)

Prescaler and divider for the

timing generator

Stack Pointer (SP)

Not initialized

General-purpose Registers

(W, A, B, C, D, E, H, L)

Not initialized

Watchdog timer

Enable

Jump Status Flag (JF)

Zero Flag (ZF)

Not initialized

Output latch of input/output port

See description of

each input/output

port.

Carry Flag (CF)

Not initialized

Half Carry Flag (HF)

Not initialized

Sign Flag (SF)

Not initialized

Overflow Flag (VF)

Not initialized

Interrupt Master Enable Flag (IMF)

Interrupt Individual Enable Flag (EF)

Control register

See description of

each control

Interrupt Latch (IL)

Interrupt Nesting Flag (INF)

RAM

Not initialized

Reset input

VDD

RESET

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