TMP88CS42FG datasheet(24/216 Pages) TOSHIBA

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Page 14

2. Functional Description

2.1 Functions of the CPU Core

TMP88CS42FG

2.1.4.3 Standby Control Circuit

The Standby Control Circuit starts/stops the high-frequency clock oscillator circuit and selects the main

system clock. The System Control Registers (SYSCR1, SYSCR2) are used to control operation modes of

this circuit. Figure 2-6 shows an operation mode transition diagram, followed by description of the Sys-

tem Control Registers.

(1) Single clock mode

Only the high-frequency clock oscillator circuit is used. Because the main system clock is gener-

ated from the high-frequency clock, the machine cycle time in single clock mode is 4/fc [s].

1. NORMAL mode

In this mode, the CPU core and peripheral hardware units are operated with the high-fre-

quency clock. The TMP88CS42FG enters this NORMAL mode after reset.

2. IDLE mode

In this mode, the CPU and watchdog timer are turned off while the peripheral hardware

units are operated with the high-frequency clock. IDLE mode is entered into by using System

Control Register 2. The device is placed out of this mode and back into NORMAL mode by

an interrupt from the peripheral hardware or an external interrupt. When IMF (interrupt mas-

ter enable flag) = 1 (interrupt enabled), the device returns to normal operation after the inter-

rupt has been serviced. When IMF = 0 (interrupt disabled), the device restarts execution

beginning with the instruction next to one that placed it in IDLE mode.

3. STOP mode

The entire system operation including the oscillator circuit is halted, retaining the internal

state immediately before being stopped, with a minimal amount of power consumed.

STOP mode is entered into by using System Control Register 1, and is exited by STOP pin

input (level or edge selectable). After an elapse of the warm-up time, the device restarts exe-

cution beginning with the instruction next to one that placed it in STOP mode.

Figure 2-6 Operation Mode Transition Diagram

Table 2-1 Single Clock Mode

Operation Mode

Oscillator Circuit

CPU Core

Peripheral

Circuit

Machine Cycle

Time

High

Frequency

Low

Frequency

Single

Clock

RESET

Oscillate

Reset

4/fc [s]

NORMAL

Operate

IDLE

Stop

STOP

Stop

RESET

STOP

mode

NORMAL

mode

IDLE

mode

Interrupt

Instruction

Input for releasing mode

Instruction

Reset deasserted

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