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ATA6560 Datasheet(PDF) 12 Page - Microchip Technology |
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ATA6560 Datasheet(HTML) 12 Page - Microchip Technology |
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12 / 28 page ![]() ATA6560/1 DS20005991A-page 12 2018 Microchip Technology Inc. Differential Receiver Threshold Voltage Vth(RX)dif 0.5 0.7 0.9 V Normal and Silent modes (HSC), Vcm(CAN) =–27V to +27V 0.4 0.7 1 V Standby mode (WUC), Vcm(CAN) =–27V to +27V (Note 1) Differential Receiver Hystere- sis Voltage (HSC) Vhys(RX)dif 50 120 200 mV Normal and Silent modes (HSC), Vcm(CAN) =–27V to +27V (Note 1) Dominant Output Current IIO(dom) –100 — –35 mA VTXD =0V, t<tto(dom)TXD, VVCC =5V pin CANH, VCANH =0V 35 — 100 mA VTXD =0V, t<tto(dom)TXD, VVCC =5V pin CANL, VCANL =5V/40V Recessive Output Current IIO(rec) –5 — +5 mA Normal and Silent modes, VTXD =VVIO, no load, VCANH =VCANL = –27V to +32V Leakage Current IIO(rec) –5 0 +5 µA VVCC =VVIO =0V, VCANH =VCANL =5V Input Resistance Ri 915 28 kΩ Input Resistance Deviation ΔRi –1 0 +1 % Between VCANH and VCANL Differential Input Resistance Ri(dif) 19 30 56 kΩ Ri(dif) 20 30 56 kΩ TvJ < +125°C Common-Mode Input Capacitance Ci(cm) — — 20 pF Note 3 Differential Input Capacitance Ci(dif) — — 10 pF Note 3 Transceiver Timing, Pins CANH, CANL, TXD, and RXD, see Figure 2-1 and Figure 2-2 Delay Time from TXD to Bus Dominant td(TXD-busdom) 40 — 130 ns Normal mode (Note 2) Delay Time from TXD to Bus Recessive td(TXD-busrec) 40 — 130 ns Normal mode (Note 2) Delay Time from Bus Dominant to RXD td(busdom-RXD) 20 — 100 ns Normal and Silent modes (Note 2) Delay Time from Bus Reces- sive to RXD td(busrec-RXD) 20 — 100 ns Normal and Silent modes (Note 2) ATA6560/1 ELECTRICAL CHARACTERISTICS (CONTINUED) Electrical Specifications: TvJ = –40°C to +150°C; VVCC = 4.5V to 5.5V; VVIO = 2.8V to 5.5V; RL =60, CL = 100 pF, unless otherwise; all voltages are defined in relation to ground; positive currents flow into the IC. Parameters Sym. Min. Typ. Max. Units Conditions Note 1: This parameter is 100% correlation tested. 2: This parameter is ensured by characterization on samples. 3: This parameter is ensured by design. |
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