AX88780_07 datasheet(11/55 Pages) ASIX

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AX88780

ASIX ELECTRONICS CORPORATION

2.4 Regulator Interface

Table 3: Regulator signals group

Pin Name

Type

Pin No.

Pin Description

VCC33R

VCC3

3.3V power to internal regulator

GNDR

GND

Ground pin for internal regulator

REG_EN

High to enable internal regulator. Low to disable internal regulator.

V25OUT

2.5V output from internal regulator, max 250mA, when REG_EN pin is high.

2.5 10/100M PHY Interface

Table 4: 10/100M Twisted-pair signals group

Pin Name

Type

Pin No.

Pin Description

RXIN

Differential received input signal for both 10BASE-T and 100BSE-TX modes.

(Note: please refer to Section 6.1.7 for detailed Transmission Characteristics)

RXIP

Differential received input signal for both 10BASE-T and 100BSE-TX modes.

TXON

Differential transmitted output signal for both 10BASE-T and 100BASE-TX modes.

(Note: please refer to Section 6.1.6 for detailed Reception Characteristics)

TXOP

Differential transmitted output signal for both 10BASE-T and 100BASE-TX modes

2.6 MII Interface

Table 5: MII Interface signals group

Pin Name

Type

Pin No.

Pin Description

TXEN

O2, 12mA

Transmit Enable:

TXEN is transition synchronously with respect to the rising edge of TXCLK. TXEN

indicates that the port is presenting nibbles on TXD [3:0] for transmission.

TXD[3:0]

O2, 12mA

61,62,

63,65

Transmit Data:

TXD[3:0] is transition synchronously with respect to the rising edge of TXCLK.

TXCLK

Transmit Clock:

TXCLK is a continuous clock from PHY. It provides the timing reference for the

transfer of the TXEN and TXD[3:0] signals from the MII port of PHY.

RXCLK

Receive Clock:

RXCLK is a continuous clock from PHY. It provides the timing reference for the

transfer of the RXDV, RXD[3:0] signals from MII port of PHY.

RXD[3:0]

77,76,75,

Receive Data:

RXD[3:0] is driven by the PHY synchronously with respect to RXCLK.

RXDV

Receive Data Valid:

RXDV is driven by the PHY synchronously with respect to RXCLK.

Asserted high

when valid data is present on RXD [3:0].

COL

Collision signal:

This signal is driven by PHY when collision is detected.

CRS

Carrier Sense:

Asynchronous signal CRS is asserted by the PHY when either the transmitted or

receive medium is non-idle.

MDIO

IO2,

8mA,PU

Station Management Data Input /Output:

Serial data input/Output transfers from/to the PHY. The transfer protocol conforms to

the IEEE 802.3u MII specification.

MDC

O2, 8mA

Station Management Data Clock:

The timing reference for MDIO. All data transfers on MDIO are synchronized to the

rising edge of this clock.

PHYINTN

An interrupt signal from PHY, active low.

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