AX88780_07 datasheet(30/55 Pages) ASIX

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AX88780

ASIX ELECTRONICS CORPORATION

4.34 MDCLKPAT--MDC Clock Pattern Register

Offset Address = 0xFCA0

Default = 0x0000_8040

Field

Name

Type

Default

Description

31:16

All 0’s

Reserved

15:8

R/W

0x80

Reserved, must set to 0x80 for normal operation

7:0

MDCPAT R/W

0x40

MDC Clock Divide Factor

This field defines the divide factor of host clock. AX88780 will refer to this field

and generate a low speed clock to PHY.

4.35 RXCHKSUMCNT--RX IP/UDP/TCP Checksum Error Counter

Offset Address = 0xFCA4

Default = 0x0000_0000

Field

Name

Type

Default

Description

31:16

All 0’s Reserved

15:0

RXCHKERCNT R/W

All 0’s RX Checksum Error Counter

If the RXCHKSUM field of RX_CFG register is set to ‘1’, MAC will check the

checksum of IP, TCP or UDP packet. Whenever there is checksum error

detected, this field will be added one. The value will be rounded back to 0x0000

if it exceeds 0xFFFF.

4.36 RXCRCNT--RX CRC Error Counter

Offset Address = 0xFCA8

Default = 0x0000_0000

Field

Name

Type

Default

Description

31:16

All 0’s

Reserved

15:0

RXCRCCNT R/W

All 0’s

RX CRC32 Error Counter

MAC checks the received packet. If there is a CRC error detect, this field will

be added one. The value will be rounded back to 0x0000 if it exceeds 0xFFFF.

4.37 TXFAILCNT--TX Fail Counter

Offset Address = 0xFCAC

Default = 0x0000_0000

Field

Name

Type

Default

Description

31:16

All 0’s

Reserved

15:0

TXFILCNT R/W

All 0’s

TX Fail Counter

This field records the number of transmitted error for TX packet. The value will

be rounded back to 0x0000 if it exceeds 0xFFFF.

4.38 PROMDPR--EEPROM Data Port Register

Offset Address = 0xFCB0h

Default = 0x0000_0000

Field

Name

Type

Default

Description

31:16

All 0’s

Reserved

15:0

PROMDP R/W

All 0’s

EEPROM Data Port

The data to or from EEPROM is set in this field.

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