ADE9178 datasheet(87/122 Pages) AD

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Data Sheet

ADE9178

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Rev. A | 87 of 122

Table 34. ADE9178 Register Details (Continued)

Addr

Name

Bits

Bit Name

Settings

Description

Reset

Access

CRC_SWELLONE_CYC_EN

CRC SWELLONE_CYC

Enable. Set this bit to

include the xSWELLONE_CYC

registers of all ADC channels in

the configuration register CRC

calculation.

0x0

R/W

CRC_SWELLONE_LVL_EN

CRC SWELLONE_LVL Enable.

Set this bit to include the

xSWELLONE_LVL registers of

all ADC channels in the

configuration register CRC

calculation.

0x0

R/W

CRC_SWELLHALF_CYC_EN

CRC SWELLHALF_CYC

Enable. Set this bit to include

the xSWELLHALF_CYC

registers of all ADC channels in

the configuration register CRC

calculation.

0x0

R/W

CRC_SWELLHALF_LVL_EN

CRC SWELLHALF_LVL

Enable. Set this bit to

include the xSWELLHALF_LVL

registers of all ADC channels in

the configuration register CRC

calculation.

0x0

R/W

CRC_DIPONE_CYC_EN

CRC DIPONE_CYC Enable.

Set this bit to include the

xDIPONE_CYC registers of

all ADC channels in the

configuration register CRC

calculation.

0x0

R/W

CRC_DIPONE_LVL_EN

CRC DIPONE_LVL Enable.

Set this bit to include the

xDIPONE_LVL registers of

all ADC channels in the

configuration register CRC

calculation.

0x0

R/W

CRC_DIPHALF_CYC_EN

CRC DIPHALF_CYC Enable.

Set this bit to include the

xDIPHALF_CYC registers of

all ADC channels in the

configuration register CRC

calculation.

0x0

R/W

CRC_DIPHALF_LVL_EN

CRC DIPHALF_LVL Enable.

Set this bit to include the

xDIPHALF_LVL registers of

all ADC channels in the

configuration register CRC

calculation.

0x0

R/W

CRC_MASK3_EN

CRC MASK3 Enable. Set this

bit to include the MASK3

0x0

R/W

CRC_MASK2_EN

CRC MASK2 Enable. Set this

bit to include the MASK2

0x0

R/W

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