ADE9178 datasheet(97/122 Pages) AD

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Data Sheet

ADE9178

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Rev. A | 97 of 122

Table 34. ADE9178 Register Details (Continued)

Addr

Name

Bits

Bit Name

Settings

Description

Reset

Access

RMSONERDY

One-Cycle RMS Data Ready.

This bit is set when the one-

cycle RMS values are updated.

0x0

R/W1C

CF2

CF2 Pulse Issued. This bit

is set when a CF2 pulse is

issued, when the CF2 pin goes

from a high to low state.

0x0

R/W1C

CF1

CF1 Pulse Issued. This bit

is set when a CF1 pulse is

issued, when the CF1 pin goes

from a high to low state.

0x0

R/W1C

REVPSUM2

CF2 Polarity Sign Change. This

bit is set to indicate if the

CF2 polarity changed sign. See

REVPSUM1.

0x0

R/W1C

REVPSUM1

CF1 Polarity Sign Change. This

bit is set to indicate if the

CF1 polarity changed sign. For

example, if the last CF1 pulse

was positive active energy

and the next CF1 pulse is

negative active energy, then

REVPSUM1 bit is set. This bit

is updated when the CF1 pin

goes from high to low.

0x0

R/W1C

REVAPC

Phase C Active Power Sign

Change. This bit indicates if

the phase C active power has

changed sign. See REVAPA.

0x0

R/W1C

REVAPB

Phase B Active Power Sign

Change. This bit indicates if

the phase B active power has

changed sign. See REVAPA.

0x0

R/W1C

REVAPA

Phase A Active Power Sign

Change. This bit indicates

if the phase A active

power has changed sign.

This bit is updated when

the power values in the

xWATT_ACC registers update,

after (EGY_TIME + 1)

milliseconds or half-line cycles.

0x0

R/W1C

EGYRDY

Energy Data Ready. This

bit is set when the

accumulated energy values

(xWATTHR, xVAHR …) are

updated, after (EGY_TIME +

1) milliseconds or half-line

cycles, which depends on the

EGY_TMR_MODE bit in the

EP_CFG register.

0x0

R/W1C

0x402

STATUS2

RESERVED

Reserved.

0x0

VACSWELLONE

VP2P Swell Condition

Detected. This bit is set when

the VP2P (AV − CV) voltage

0x0

R/W1C

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