ADE9178 datasheet(100/122 Pages) AD

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Data Sheet

ADE9178

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Rev. A | 100 of 122

Table 34. ADE9178 Register Details (Continued)

Addr

Name

Bits

Bit Name

Settings

Description

Reset

Access

swell condition, as calculated

by RMSONE.

AISWELLONE

Phase A Current Swell

Condition Detected. This bit is

set when the phase A current

is in the swell condition and

is zero when it is not in a

swell condition, as calculated

by RMSONE.

0x0

R/W1C

AVSWELLONE

Phase A Voltage Swell

Condition Detected. This bit is

set when the phase A voltage

is in the swell condition and

is zero when it is not in a

swell condition, as calculated

by RMSONE.

0x0

R/W1C

AUX5DIPONE

Auxiliary 5 Channel Dip

Condition Detected. This bit is

set when the AUX5 channel is

in the dip condition and is zero

when it is not in a dip condition,

as calculated by RMSONE.

0x0

R/W1C

AUX4DIPONE

Auxiliary 4 Channel Dip

Condition Detected. This bit is

set when the AUX4 channel is

in the dip condition and is zero

when it is not in a dip condition,

as calculated by RMSONE.

0x0

R/W1C

AUX3DIPONE

Auxiliary 3 Channel Dip

Condition Detected. This bit is

set when the AUX3 channel is

in the dip condition and is zero

when it is not in a dip condition,

as calculated by RMSONE.

0x0

R/W1C

AUX2DIPONE

Auxiliary 2 Channel Dip

Condition Detected. This bit is

set when the AUX2 channel is

in the dip condition and is zero

when it is not in a dip condition,

as calculated by RMSONE.

0x0

R/W1C

AUX1DIPONE

Auxiliary 1 Channel Dip

Condition Detected. This bit is

set when the AUX1 channel is

in the dip condition and is zero

when it is not in a dip condition,

as calculated by RMSONE.

0x0

R/W1C

AUX0DIPONE

Auxiliary 0 Channel Dip

Condition Detected. This bit is

set when the AUX0 channel is

in the dip condition and is zero

when it is not in a dip condition,

as calculated by RMSONE.

0x0

R/W1C

CIDIPONE

Phase C Current Dip Condition

Detected. This bit is set when

the phase C current is in the

0x0

R/W1C

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