ADE9178 datasheet(98/122 Pages) AD

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Data Sheet

ADE9178

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Rev. A | 98 of 122

Table 34. ADE9178 Register Details (Continued)

Addr

Name

Bits

Bit Name

Settings

Description

Reset

Access

is in the swell condition and

is zero when it is not in a

swell condition, as calculated

by RMSONE.

VBCSWELLONE

VP2P Swell Condition

Detected. This bit is set when

the VP2P (BV − CV) voltage

is in the swell condition and

is zero when it is not in a

swell condition, as calculated

by RMSONE.

0x0

R/W1C

VABSWELLONE

VP2P Swell Condition

Detected. This bit is set when

the VP2P (AV − BV) voltage

is in the swell condition and

is zero when it is not in a

swell condition, as calculated

by RMSONE.

0x0

R/W1C

VACDIPONE

VP2P Dip Condition Detected.

This bit is set when the VP2P

(AV − CV) voltage is in the dip

condition and is zero when it

is not in a dip condition, as

calculated by RMSONE.

0x0

R/W1C

VBCDIPONE

VP2P Dip Condition Detected.

This bit is set when the VP2P

(BV − CV) voltage is in the

dip condition and is zero when

it is not in a dip condition, as

calculated by RMSONE.

0x0

R/W1C

VABDIPONE

VP2P Dip Condition Detected.

This bit is set when the VP2P

(AV − BV) voltage is in the dip

condition and is zero when it

is not in a dip condition, as

calculated by RMSONE.

0x0

R/W1C

VSUMSWELLONE

VSUM Swell Condition

Detected. This bit is set when

the sum of voltage channels

is in the swell condition and

is zero when it is not in a

swell condition, as calculated

by RMSONE.

0x0

R/W1C

AUX5SWELLONE

Auxiliary 5 Channel Swell

Condition Detected. This bit is

set when the AUX5 channel

is in the swell condition and

is zero when it is not in a

swell condition, as calculated

by RMSONE.

0x0

R/W1C

AUX4SWELLONE

Auxiliary 4 Channel Swell

Condition Detected. This bit is

set when the AUX4 channel

is in the swell condition and

is zero when it is not in a

0x0

R/W1C

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