ADE9178 datasheet(107/122 Pages) AD

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Data Sheet

ADE9178

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Rev. A | 107 of 122

Table 34. ADE9178 Register Details (Continued)

Addr

Name

Bits

Bit Name

Settings

Description

Reset

Access

to enable an interrupt when a

zero crossing is detected on

the phase B voltage channel.

ZXAV

Phase A Voltage Zero Crossing

Detected Mask. Set this bit

to enable an interrupt when a

zero crossing is detected on

the phase A voltage channel.

0x0

R/W

ZXTOCV

Phase C Voltage Zero-

Crossing Timeout Mask. Set

this bit to enable an interrupt

when there is a zero-crossing

timeout on phase C. This

means that a zero crossing on

the phase C voltage is missing.

0x0

R/W

ZXTOBV

Phase B Voltage Zero-Crossing

Timeout Mask. Set this bit to

enable an interrupt when there

is a zero-crossing timeout on

phase B. This means that a

zero crossing on the phase B

voltage is missing.

0x0

R/W

ZXTOAV

Phase A Voltage Zero-Crossing

Timeout Mask. Set this bit to

enable an interrupt when there

is a zero-crossing timeout on

phase A. This means that a

zero crossing on the phase A

voltage is missing.

0x0

R/W

SEQERR

Phase Sequence Error

Occurred on Voltage Zero

Crossings. Set this bit to

enable an interrupt when zero

crossings on three voltage

phases does not follow phase

A − phase B − phase C

sequence.

0x0

R/W

RSTDONE

Reset Completed and Ready

for SPI Communication. Set

this bit to enable an interrupt

when the reset is complete

and board is ready for SPI

communication.

0x1

CRC_CHG

CRC Changed Mask. Set this

bit to enable an interrupt if

any of the registers monitored

by the configuration register

CRC change value. The

CRC_RSLT register holds the

new configuration register CRC

value.

0x0

R/W

VANLOAD

Total Apparent Energy No Load

Condition Changed Mask. Set

this bit to enable an interrupt

when one or more phase of

0x0

R/W

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