LMH0026

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SNLS253B – MARCH 2008 – REVISED APRIL 2013

DC ELECTRICAL CHARACTERISTICS (continued)

Over Supply Voltage and Operating Temperature ranges, unless otherwise specified.

(1)(2)

Symbol

Parameter

Conditions

Reference

Min

Typ

Max

Units

VSDOD

Serial Output Voltage,

100

Ω differential load

SDO, SCO

720

800

880

mVP-P

Differential

VCMO

Output Common Mode

100

Ω differential load

VCC−

V

Voltage

VSDOD

ICC

Power Supply Current,

270 Mbps

100

mA

3.3V supply, Total

AC ELECTRICAL CHARACTERISTICS

Over Supply Voltage and Operating Temperature ranges, unless otherwise specified.

(1)

Symbol

Parameter

Conditions

Reference

Min

Typ

Max

Units

BRSD

Serial Data Rate

SMPTE 259M-C

SDI, SDO

270

Mbps

TOLJIT

Serial Input Jitter

270 Mbps,

SDI

>6

UIP-P

Tolerance

(2) (3) (4)

TOLJIT

Serial Input Jitter

270 Mbps, (2) (3) (5)

>0.6

UIP-P

Tolerance

tJIT

Serial Data Output Jitter

270 Mbps, (3) (6)

SDO

0.02

0.08

UIP-P

BWLOOP

Loop Bandwidth

270 Mbps,

300

kHz

<0.1dB Peaking

FCO

Serial Clock Output

270 Mbps data rate

SCO

270

MHz

Frequency

tJIT

Serial Clock Output Jitter

2

3

psRMS

Serial Clock Output

SDO, SCO

Alignment with respect to

40

60

%

Data Interval

Serial Clock Output Duty

SCO

45

55

%

Cycle

TACQ

Acquisition Time

(7) (8)15

ms

tr, tf

Input rise/fall time

10%–90%

Logic inputs

1.5

3

ns

tr, tf

Input rise/fall time

20%–80%

SDI

1500

ps

tr, tf

Output rise/fall time

10%–90%

Logic outputs

1.5

3

ns

tr, tf

Output rise/fall time

20%–80%, (9)

SDO, SCO

90

130

ps

FREF

Reference Clock

27

MHz

Frequency

FTOL

Reference Clock

±50

ppm

Frequency Tolerance

(1)

Typical values are stated for: VCC = +3.3V, TA = +25°C.

(2)

Peak-to-peak amplitude with sinusoidal modulation per SMPTE RP 184-1996 paragraph 4.1. The test data signal shall be color bars.

(3)

This parameter is ensured by characterization over voltage and temperature limits.

(4)

Refer to “A1” in Figure 1 of SMPTE RP 184-1996.

(5)

Refer to “A2” in Figure 1 of SMPTE RP 184-1996.

(6)

Serial Data Output Jitter is total output jitter with 0.2 UIP-P input jitter.

(7)

Specification is ensured by design.

(8)

Measured from first SDI transition until Lock Detect (LD) output goes high (true).

(9)

RL = 100Ω differential.

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