LMH0026

SNLS253B – MARCH 2008 – REVISED APRIL 2013

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The LMH0026 inputs are LVPECL compatible. The LMH0026 has a wide input common mode range and in most

cases the input should be DC coupled. For DC coupling, the inputs must be kept within the common mode range

specified in DC ELECTRICAL CHARACTERISTICS. Figure 5 shows an example of a DC coupled interface

between the LMH0074 cable equalizer and the LMH0026. The LMH0074 output common mode voltage and

voltage swing are within the range of the input common mode voltage and voltage swing of the LMH0026. All

that is required is a 100

Ω differential termination as shown. The resistor should be placed as close to the

LMH0026 input as possible. If desired, this network may be terminated with two 50

Ω resisters and a center tap

capacitor to ground in place of the single 100

Ω resistor.

The LMH0026 outputs are LVPECL compatible. SDO is the primary data output and SCO/SDO2 is a second

output that may be set as the serial clock or a second data output. Both outputs are always active. The LMH0026

output should be DC coupled to the input of the receiving device as long as the common mode ranges of both

devices are compatible. Figure 5 shows an example of a DC coupled interface between the LMH0026 and

LMH0001 cable driver. All that is required is a 100

Ω differential termination as shown. The resistor should be

placed as close to the LMH0001 input as possible. If desired, this network may be terminated with two 50

Ω

resisters and a center tap capacitor to ground in place of the single 100

Ω resistor.

The external loop filter capacitor (between LF1 and LF2) should be 56 nF. This is the only supported value; the

loop filter capacitor should not be changed.

BYPASS/AUTO BYPASS has an internal pulldown to enable Auto Bypass mode by default. This pin may be

pulled high to force the LMH0026 to bypass all data.

OUTPUT MUTE has an internal pullup to enable the outputs by default. This pin may be pulled low to mute the

outputs.

The XTAL IN/EXT CLK and XTAL OUT pins are shown with a 27 MHz crystal and the proper loading. The crystal

should match the parameters described in Table 2. Alternately, a 27MHz LVCMOS compatible clock signal may

be input to XTAL IN/EXT CLK.

The active high LOCK DETECT output provides an indication that proper data is being received and the PLL is

locked.

The SD output may be used to drive the SD/HD pin of an SDI cable driver (such as the LMH0002) in order to

properly set the cable driver’s edge rate for SMPTE compliance. It defaults to low when the LMH0026 is not

locked.

SCO_EN has an internal pulldown to set the second output (SCO/SDO2) to output data. This pin may be pulled

high to set the second output as a serial clock.

The ground connection for the LMH0026 is through the large exposed DAP. The DAP must be connected to

ground for proper operation of the LMH0026.

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